diff options
| author | Schuyler Eldridge | 2018-11-07 15:30:17 -0500 |
|---|---|---|
| committer | GitHub | 2018-11-07 15:30:17 -0500 |
| commit | 75284395ba7ef285daefd2da38e720590b465ad7 (patch) | |
| tree | 7ae4e04a16eb87ce306a9d891acabbd4c6b1c8b7 /src/main/scala/firrtl/passes/memlib/MemLibOptions.scala | |
| parent | 17b4e9835bd95dcf91c5ea5a4d7c52280031ea93 (diff) | |
| parent | b05eaea3e59c64d619a544c63311d510f335f7e5 (diff) | |
Merge pull request #919 from seldridge/f764.6
- Add, but do not use Options-mirroring Annotations
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemLibOptions.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemLibOptions.scala | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala new file mode 100644 index 00000000..2f26e4e5 --- /dev/null +++ b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala @@ -0,0 +1,15 @@ +// See LICENSE for license details. + +package firrtl.passes.memlib + +import firrtl._ +import firrtl.options.RegisteredLibrary +import scopt.OptionParser + +class MemLibOptions extends RegisteredLibrary { + val name: String = "MemLib Options" + def addOptions(p: OptionParser[AnnotationSeq]): Unit = + Seq( new InferReadWrite, + new ReplSeqMem ) + .map(_.addOptions(p)) +} |
