diff options
| author | Albert Magyar | 2019-02-01 11:01:35 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2019-02-01 11:01:35 -0800 |
| commit | 6b59614462ae8591db999fef9ba0d451e56d1c24 (patch) | |
| tree | 95c8ba8e9a1135fce36f24a5416a16e5e8a93263 /src/main/scala/firrtl/passes/memlib/MemIR.scala | |
| parent | 4e77c5e14a05cedda621a4acdbc435bed23a202d (diff) | |
Mem helpers (#1010)
* Add memory WRef factory for completeness
* Refactor DefAnnotatedMemory construction for clarity
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemIR.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemIR.scala | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala index a7ef9d43..55f0f571 100644 --- a/src/main/scala/firrtl/passes/memlib/MemIR.scala +++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala @@ -7,6 +7,25 @@ import firrtl._ import firrtl.ir._ import Utils.indent +object DefAnnotatedMemory { + def apply(m: DefMemory): DefAnnotatedMemory = { + new DefAnnotatedMemory( + m.info, + m.name, + m.dataType, + m.depth, + m.writeLatency, + m.readLatency, + m.readers, + m.writers, + m.readwriters, + m.readUnderWrite, + None, // mask granularity annotation + None // No reference yet to another memory + ) + } +} + case class DefAnnotatedMemory( info: Info, name: String, |
