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authorSchuyler Eldridge2020-06-19 01:11:15 -0400
committerSchuyler Eldridge2020-06-22 19:00:20 -0400
commitd66ff2357e59113ecf48c7d257edff429c4266e0 (patch)
tree30f5d068ea78caf172008f900e3d4fde7e20f6b0 /src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
parent2d1e074a67483c136d5f0ed86e8ecf1b8505bc10 (diff)
Convert PreservesAll to explicit invalidates=false
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala')
-rw-r--r--src/main/scala/firrtl/passes/memlib/InferReadWrite.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index ddcf9483..03c295ed 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -8,7 +8,7 @@ import firrtl.ir._
import firrtl.Mappers._
import firrtl.PrimOps._
import firrtl.Utils.{one, zero, BoolType}
-import firrtl.options.{HasShellOptions, PreservesAll, ShellOption}
+import firrtl.options.{HasShellOptions, ShellOption}
import MemPortUtils.memPortField
import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin}
import WrappedExpression.weq
@@ -146,13 +146,13 @@ object InferReadWritePass extends Pass {
// To use this transform, circuit name should be annotated with its TransId.
class InferReadWrite extends Transform
with DependencyAPIMigration
- with PreservesAll[Transform]
with SeqTransformBased
with HasShellOptions {
override def prerequisites = Forms.MidForm
override def optionalPrerequisites = Seq.empty
override def optionalPrerequisiteOf = Forms.MidEmitters
+ override def invalidates(a: Transform) = false
val options = Seq(
new ShellOption[Unit](