diff options
| author | Leway Colin | 2019-07-09 01:41:02 +0800 |
|---|---|---|
| committer | mergify[bot] | 2019-07-08 17:41:02 +0000 |
| commit | aa571e1d4f76d095344a9deed28dfa70f704fa75 (patch) | |
| tree | 77e34d92f04f32f7c3c28bde8c9dac2892943ac5 /src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | |
| parent | 648dddeacd9aece4a43cad09430dad25cba69457 (diff) | |
Remove some warnings (#1118)
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 1663efaa..44f45985 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -85,8 +85,6 @@ object InferReadWritePass extends Pass { (s: Statement): Statement = s match { // infer readwrite ports only for non combinational memories case mem: DefMemory if mem.readLatency > 0 => - val ut = UnknownType - val ug = UNKNOWNGENDER val readers = new PortSet val writers = new PortSet val readwriters = collection.mutable.ArrayBuffer[String]() |