diff options
| author | Donggyu | 2016-10-26 16:38:28 -0700 |
|---|---|---|
| committer | GitHub | 2016-10-26 16:38:28 -0700 |
| commit | 1c61a0e7102983891d99d8e9c49e331c8a2178a6 (patch) | |
| tree | 038ad4dae9f0d17ba4a5a7bdf582cbe75ccdd2e5 /src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | |
| parent | 4c3b4f4dc10c380a101df75cb561e3f79f1a6abe (diff) | |
Improve reference & name resolution in ReplSeqMem (#352)
* fix imports in InferReadWrite
* improve reference & name resolution in ReplSeqMem
* add comments
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 9adbdd95..ffdea1f2 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -32,9 +32,8 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} -import firrtl.passes.memlib._ import MemPortUtils.memPortField -import AnalysisUtils.{Connects, getConnects, getOrigin} +import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq import Annotations._ |