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| author | Schuyler Eldridge | 2019-07-17 14:08:33 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-09-16 17:12:51 -0400 |
| commit | a594ccef986c4567730fee729bdea9ed9aefed38 (patch) | |
| tree | 2512913e054ea7d56867f2c73912ff4be17f1e82 /src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
Rename gender to flow
The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 44f45985..1e88a9b0 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -160,7 +160,7 @@ class InferReadWrite extends Transform with SeqTransformBased with HasShellOptio CheckInitialization, InferTypes, ResolveKinds, - ResolveGenders + ResolveFlows ) def execute(state: CircuitState): CircuitState = { val runTransform = state.annotations.contains(InferReadWriteAnnotation) |