Use scalafix to remove unused import and deprecated procedure syntax (#1074)

* Add sbt-scalafix

* Add scalafix guide to README

* Remove Unused Import

* Remove deprecated procedure syntax

4 files changed, 2 insertions, 21 deletions

diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index 984fd813..c2323d4c 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -6,14 +6,11 @@ package clocklist
 import firrtl._
 import firrtl.ir._
 import annotations._
-import Utils.error
-import java.io.{File, CharArrayWriter, PrintWriter, Writer}
+import java.io.{CharArrayWriter, Writer}
 import wiring.WiringUtils.{getChildrenMap, getLineage}
-import wiring.Lineage
 import ClockListUtils._
 import Utils._
 import memlib.AnalysisUtils._
-import memlib._
 
 /** Starting with a top module, determine the clock origins of each child instance.
  *  Write the result to writer.
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index f95787bd..26003954 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -4,17 +4,12 @@ package firrtl.passes
 package clocklist
 
 import firrtl._
-import firrtl.ir._
 import annotations._
 import Utils.error
-import java.io.{File, CharArrayWriter, PrintWriter, Writer}
-import wiring.Lineage
-import ClockListUtils._
+import java.io.{PrintWriter, Writer}
 import Utils._
-import memlib.AnalysisUtils._
 import memlib._
 import firrtl.options.{RegisteredTransform, ShellOption}
-import scopt.OptionParser
 import firrtl.stage.RunFirrtlTransformAnnotation
 
 case class ClockListAnnotation(target: ModuleName, outputConfig: String) extends
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
index 2cc3dd5c..f92a878e 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
@@ -5,14 +5,9 @@ package clocklist
 
 import firrtl._
 import firrtl.ir._
-import annotations._
-import Utils.error
-import java.io.{File, CharArrayWriter, PrintWriter, Writer}
 import wiring.Lineage
-import ClockListUtils._
 import Utils._
 import memlib.AnalysisUtils._
-import memlib._
 
 object ClockListUtils {
   /** Returns a list of clock outputs from instances of external modules
diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
index 1178ce69..6eb8c138 100644
--- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
+++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
@@ -5,13 +5,7 @@ package clocklist
 
 import firrtl._
 import firrtl.ir._
-import annotations._
-import Utils.error
-import java.io.{File, CharArrayWriter, PrintWriter, Writer}
-import ClockListUtils._
 import Utils._
-import memlib.AnalysisUtils._
-import memlib._
 import Mappers._
 
 /** Remove all statements and ports (except instances/whens/blocks) whose