diff options
| author | Schuyler Eldridge | 2019-07-17 14:08:33 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-09-16 17:12:51 -0400 |
| commit | a594ccef986c4567730fee729bdea9ed9aefed38 (patch) | |
| tree | 2512913e054ea7d56867f2c73912ff4be17f1e82 /src/main/scala/firrtl/passes/clocklist | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
Rename gender to flow
The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/clocklist')
| -rw-r--r-- | src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala index f92a878e..b77629fc 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala @@ -20,8 +20,8 @@ object ClockListUtils { } val sourceList = moduleMap(lin.name) match { case ExtModule(i, n, ports, dn, p) => - val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction)))} - portExps.filter(e => (e.tpe == ClockType) && (gender(e) == FEMALE)).map(_.serialize) + val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction)))} + portExps.filter(e => (e.tpe == ClockType) && (flow(e) == SinkFlow)).map(_.serialize) case _ => Nil } val sx = sourceList ++ s |