All of src/ formatted with scalafmt

4 files changed, 62 insertions, 48 deletions

diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index c2323d4c..bfc03b51 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -13,8 +13,8 @@ import Utils._
 import memlib.AnalysisUtils._
 
 /** Starting with a top module, determine the clock origins of each child instance.
- *  Write the result to writer.
- */
+  *  Write the result to writer.
+  */
 class ClockList(top: String, writer: Writer) extends Pass {
   def run(c: Circuit): Circuit = {
     // Build useful datastructures
@@ -29,7 +29,7 @@ class ClockList(top: String, writer: Writer) extends Pass {
 
     // Clock sources must be blackbox outputs and top's clock
     val partialSourceList = getSourceList(moduleMap)(lineages)
-    val sourceList = partialSourceList ++ moduleMap(top).ports.collect{ case Port(i, n, Input, ClockType) => n }
+    val sourceList = partialSourceList ++ moduleMap(top).ports.collect { case Port(i, n, Input, ClockType) => n }
     writer.append(s"Sourcelist: $sourceList \n")
 
     // Remove everything from the circuit, unless it has a clock type
@@ -37,8 +37,9 @@ class ClockList(top: String, writer: Writer) extends Pass {
     val onlyClockCircuit = RemoveAllButClocks.run(c)
 
     // Inline the clock-only circuit up to the specified top module
-    val modulesToInline = (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet
-    val inlineTransform = new InlineInstances{ override val inlineDelim = "$" }
+    val modulesToInline =
+      (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet
+    val inlineTransform = new InlineInstances { override val inlineDelim = "$" }
     val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), Seq()).circuit
     val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError("no top module"))
 
@@ -49,13 +50,14 @@ class ClockList(top: String, writer: Writer) extends Pass {
     val origins = getOrigins(connects, "", moduleMap)(lineages)
 
     // If the clock origin is contained in the source list, label good (otherwise bad)
-    origins.foreach { case (instance, origin) =>
-      val sep = if(instance == "") "" else "."
-      if(!sourceList.contains(origin.replace('.','$'))){
-        outputBuffer.append(s"Bad Origin of $instance${sep}clock is $origin\n")
-      } else {
-        outputBuffer.append(s"Good Origin of $instance${sep}clock is $origin\n")
-      }
+    origins.foreach {
+      case (instance, origin) =>
+        val sep = if (instance == "") "" else "."
+        if (!sourceList.contains(origin.replace('.', '$'))) {
+          outputBuffer.append(s"Bad Origin of $instance${sep}clock is $origin\n")
+        } else {
+          outputBuffer.append(s"Good Origin of $instance${sep}clock is $origin\n")
+        }
     }
 
     // Write to output file
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index e6617857..468ba905 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -12,8 +12,7 @@ import memlib._
 import firrtl.options.{RegisteredTransform, ShellOption}
 import firrtl.stage.{Forms, RunFirrtlTransformAnnotation}
 
-case class ClockListAnnotation(target: ModuleName, outputConfig: String) extends
-    SingleTargetAnnotation[ModuleName] {
+case class ClockListAnnotation(target: ModuleName, outputConfig: String) extends SingleTargetAnnotation[ModuleName] {
   def duplicate(n: ModuleName) = ClockListAnnotation(n, outputConfig)
 }
 
@@ -44,7 +43,7 @@ Usage:
     )
     passOptions.get(InputConfigFileName) match {
       case Some(x) => error("Unneeded input config file name!" + usage)
-      case None =>
+      case None    =>
     }
     val target = ModuleName(passModule, CircuitName(passCircuit))
     ClockListAnnotation(target, outputConfig)
@@ -53,18 +52,20 @@ Usage:
 
 class ClockListTransform extends Transform with DependencyAPIMigration with RegisteredTransform {
 
-   override def prerequisites = Forms.LowForm
-   override def optionalPrerequisites = Seq.empty
-   override def optionalPrerequisiteOf = Forms.LowEmitters
+  override def prerequisites = Forms.LowForm
+  override def optionalPrerequisites = Seq.empty
+  override def optionalPrerequisiteOf = Forms.LowEmitters
 
   val options = Seq(
     new ShellOption[String](
       longOption = "list-clocks",
-      toAnnotationSeq = (a: String) => Seq( passes.clocklist.ClockListAnnotation.parse(a),
-                                            RunFirrtlTransformAnnotation(new ClockListTransform) ),
+      toAnnotationSeq = (a: String) =>
+        Seq(passes.clocklist.ClockListAnnotation.parse(a), RunFirrtlTransformAnnotation(new ClockListTransform)),
       helpText = "List which signal drives each clock of every descendent of specified modules",
       shortOption = Some("clks"),
-      helpValueName = Some("-c:<circuit>:-m:<module>:-o:<filename>") ) )
+      helpValueName = Some("-c:<circuit>:-m:<module>:-o:<filename>")
+    )
+  )
 
   def passSeq(top: String, writer: Writer): Seq[Pass] =
     Seq(new ClockList(top, writer))
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
index b77629fc..00e07588 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
@@ -10,45 +10,56 @@ import Utils._
 import memlib.AnalysisUtils._
 
 object ClockListUtils {
+
   /** Returns a list of clock outputs from instances of external modules
-   */
+    */
   def getSourceList(moduleMap: Map[String, DefModule])(lin: Lineage): Seq[String] = {
-    val s = lin.foldLeft(Seq[String]()){case (sL, (i, l)) =>
-      val sLx = getSourceList(moduleMap)(l)
-      val sLxx = sLx map (i + "$" + _)
-      sL ++ sLxx
+    val s = lin.foldLeft(Seq[String]()) {
+      case (sL, (i, l)) =>
+        val sLx = getSourceList(moduleMap)(l)
+        val sLxx = sLx.map(i + "$" + _)
+        sL ++ sLxx
     }
     val sourceList = moduleMap(lin.name) match {
       case ExtModule(i, n, ports, dn, p) =>
-        val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction)))}
+        val portExps = ports.flatMap { p => create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction))) }
         portExps.filter(e => (e.tpe == ClockType) && (flow(e) == SinkFlow)).map(_.serialize)
       case _ => Nil
     }
     val sx = sourceList ++ s
     sx
   }
+
   /** Returns a map from instance name to its clock origin.
-   *  Child instances are not included if they share the same clock as their parent
-   */
-  def getOrigins(connects: Connects, me: String, moduleMap: Map[String, DefModule])(lin: Lineage): Map[String, String] = {
-    val sep = if(me == "") "" else "$"
+    *  Child instances are not included if they share the same clock as their parent
+    */
+  def getOrigins(
+    connects:  Connects,
+    me:        String,
+    moduleMap: Map[String, DefModule]
+  )(lin:       Lineage
+  ): Map[String, String] = {
+    val sep = if (me == "") "" else "$"
     // Get origins from all children
-    val childrenOrigins = lin.foldLeft(Map[String, String]()){case (o, (i, l)) =>
-      o ++ getOrigins(connects, me + sep + i, moduleMap)(l)
+    val childrenOrigins = lin.foldLeft(Map[String, String]()) {
+      case (o, (i, l)) =>
+        o ++ getOrigins(connects, me + sep + i, moduleMap)(l)
     }
     // If I have a clock, get it
     val clockOpt = moduleMap(lin.name) match {
-      case Module(i, n, ports, b) => ports.collectFirst { case p if p.name == "clock" => me + sep + "clock" }
+      case Module(i, n, ports, b)        => ports.collectFirst { case p if p.name == "clock" => me + sep + "clock" }
       case ExtModule(i, n, ports, dn, p) => None
     }
     // Return new origins with direct children removed, if they match my clock
     clockOpt match {
       case Some(clock) =>
         val myOrigin = getOrigin(connects, clock).serialize
-        childrenOrigins.foldLeft(Map(me -> myOrigin)) { case (o, (childInstance, childOrigin)) =>
-          val childrenInstances = lin.children.map { case (instance, _) => me + sep + instance }
-          // If direct child shares my origin, omit it
-          if(childOrigin == myOrigin && childrenInstances.contains(childInstance)) o else o + (childInstance -> childOrigin)
+        childrenOrigins.foldLeft(Map(me -> myOrigin)) {
+          case (o, (childInstance, childOrigin)) =>
+            val childrenInstances = lin.children.map { case (instance, _) => me + sep + instance }
+            // If direct child shares my origin, omit it
+            if (childOrigin == myOrigin && childrenInstances.contains(childInstance)) o
+            else o + (childInstance -> childOrigin)
         }
       case None => childrenOrigins
     }
diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
index 6eb8c138..d72bc293 100644
--- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
+++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
@@ -9,22 +9,22 @@ import Utils._
 import Mappers._
 
 /** Remove all statements and ports (except instances/whens/blocks) whose
- *  expressions do not relate to ground types.
- */
+  *  expressions do not relate to ground types.
+  */
 object RemoveAllButClocks extends Pass {
-  def onStmt(s: Statement): Statement = (s map onStmt) match {
-    case DefWire(i, n, ClockType) => s
+  def onStmt(s: Statement): Statement = (s.map(onStmt)) match {
+    case DefWire(i, n, ClockType)                       => s
     case DefNode(i, n, value) if value.tpe == ClockType => s
-    case Connect(i, l, r) if l.tpe == ClockType => s
-    case sx: WDefInstance => sx
-    case sx: DefInstance => sx
-    case sx: Block => sx
+    case Connect(i, l, r) if l.tpe == ClockType         => s
+    case sx: WDefInstance  => sx
+    case sx: DefInstance   => sx
+    case sx: Block         => sx
     case sx: Conditionally => sx
     case _ => EmptyStmt
   }
   def onModule(m: DefModule): DefModule = m match {
-    case Module(i, n, ps, b) => Module(i, n, ps.filter(_.tpe == ClockType), squashEmpty(onStmt(b)))
+    case Module(i, n, ps, b)        => Module(i, n, ps.filter(_.tpe == ClockType), squashEmpty(onStmt(b)))
     case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps.filter(_.tpe == ClockType), dn, p)
   }
-  def run(c: Circuit): Circuit = c.copy(modules = c.modules map onModule)
+  def run(c: Circuit): Circuit = c.copy(modules = c.modules.map(onModule))
 }