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authorJack Koenig2021-12-21 18:47:18 -0800
committerGitHub2021-12-21 18:47:18 -0800
commit4f3d1003811aa38d10e32b347c8607414d9be034 (patch)
tree07db8aefae4bf9d10dc6ff523fb9c43016dcc05c /src/main/scala/firrtl/passes/ZeroWidth.scala
parent2d197c841c5400c6deaa1592525be6a1d81dc1e2 (diff)
Remove some warnings (#2448)
* Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth
Diffstat (limited to 'src/main/scala/firrtl/passes/ZeroWidth.scala')
-rw-r--r--src/main/scala/firrtl/passes/ZeroWidth.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index ab1cf7bb..057f85a6 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -204,6 +204,6 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
val renames = MutableRenameMap()
renames.setCircuit(c.main)
val result = c.copy(modules = c.modules.map(onModule(renames)))
- CircuitState(result, outputForm, state.annotations, Some(renames))
+ state.copy(circuit = result, renames = Some(renames))
}
}