Fold VerilogModulusCleanup into LegalizeVerilog (#2485)

This fixes handling of signed modulus and removes some redundant work.

1 files changed, 2 insertions, 61 deletions

diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
index 3ca862b9..d0582478 100644
--- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
+++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
@@ -4,9 +4,6 @@ package firrtl
 package passes
 
 import firrtl.ir._
-import firrtl.Mappers._
-import firrtl.PrimOps.{Bits, Rem}
-import firrtl.Utils._
 import firrtl.options.Dependency
 
 import scala.collection.mutable
@@ -24,6 +21,7 @@ import scala.collection.mutable
   *  This is technically incorrect firrtl, but allows the verilog emitter
   *  to emit correct verilog without needing to add temporary nodes
   */
+@deprecated("This pass's functionality has been moved to LegalizeVerilog", "FIRRTL 1.5.2")
 object VerilogModulusCleanup extends Pass {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
@@ -43,62 +41,5 @@ object VerilogModulusCleanup extends Pass {
 
   override def invalidates(a: Transform) = false
 
-  private def onModule(m: Module): Module = {
-    val namespace = Namespace(m)
-    def onStmt(s: Statement): Statement = {
-      val v = mutable.ArrayBuffer[Statement]()
-
-      def getWidth(e: Expression): Width = e.tpe match {
-        case t: GroundType => t.width
-        case t => UnknownWidth
-      }
-
-      def maxWidth(ws: Seq[Width]): Width = ws.reduceLeft { (x, y) =>
-        (x, y) match {
-          case (IntWidth(x), IntWidth(y)) => IntWidth(x.max(y))
-          case (x, y)                     => UnknownWidth
-        }
-      }
-
-      def verilogRemWidth(e: DoPrim)(tpe: Type): Type = {
-        val newWidth = maxWidth(e.args.map(exp => getWidth(exp)))
-        tpe.mapWidth(w => newWidth)
-      }
-
-      def removeRem(e: Expression): Expression = e match {
-        case e: DoPrim =>
-          e.op match {
-            case Rem =>
-              val name = namespace.newTemp
-              val newType = e.mapType(verilogRemWidth(e))
-              v += DefNode(get_info(s), name, e.mapType(verilogRemWidth(e)))
-              val remRef = WRef(name, newType.tpe, kind(e), flow(e))
-              val remWidth = bitWidth(e.tpe)
-              DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe)
-            case _ => e
-          }
-        case _ => e
-      }
-
-      s.map(removeRem) match {
-        case x: Block => x.map(onStmt)
-        case EmptyStmt => EmptyStmt
-        case x =>
-          v += x
-          v.size match {
-            case 1 => v.head
-            case _ => Block(v.toSeq)
-          }
-      }
-    }
-    Module(m.info, m.name, m.ports, onStmt(m.body))
-  }
-
-  def run(c: Circuit): Circuit = {
-    val modules = c.modules.map {
-      case m: Module    => onModule(m)
-      case m: ExtModule => m
-    }
-    Circuit(c.info, modules, c.main)
-  }
+  def run(c: Circuit): Circuit = c
 }