All of src/ formatted with scalafmt

1 files changed, 43 insertions, 38 deletions

diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
index 36eff379..0b046a5f 100644
--- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
+++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
@@ -12,28 +12,30 @@ import firrtl.options.Dependency
 import scala.collection.mutable
 
 /**
- * Verilog has the width of (a % b) = Max(W(a), W(b))
- * FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense,
- * but nevertheless is a problem when emitting verilog
- *
- * This pass finds every instance of (a % b) and:
- *   1) adds a temporary node equal to (a % b) with width Max(W(a), W(b))
- *   2) replaces the reference to (a % b) with a bitslice of the temporary node
- *      to get back down to width Min(W(a), W(b))
- *
- *  This is technically incorrect firrtl, but allows the verilog emitter
- *  to emit correct verilog without needing to add temporary nodes
- */
+  * Verilog has the width of (a % b) = Max(W(a), W(b))
+  * FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense,
+  * but nevertheless is a problem when emitting verilog
+  *
+  * This pass finds every instance of (a % b) and:
+  *   1) adds a temporary node equal to (a % b) with width Max(W(a), W(b))
+  *   2) replaces the reference to (a % b) with a bitslice of the temporary node
+  *      to get back down to width Min(W(a), W(b))
+  *
+  *  This is technically incorrect firrtl, but allows the verilog emitter
+  *  to emit correct verilog without needing to add temporary nodes
+  */
 object VerilogModulusCleanup extends Pass {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
-    Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper],
-         Dependency[firrtl.transforms.FixAddingNegativeLiterals],
-         Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
-         Dependency[firrtl.transforms.InlineBitExtractionsTransform],
-         Dependency[firrtl.transforms.InlineCastsTransform],
-         Dependency[firrtl.transforms.LegalizeClocksTransform],
-         Dependency[firrtl.transforms.FlattenRegUpdate] )
+    Seq(
+      Dependency[firrtl.transforms.BlackBoxSourceHelper],
+      Dependency[firrtl.transforms.FixAddingNegativeLiterals],
+      Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
+      Dependency[firrtl.transforms.InlineBitExtractionsTransform],
+      Dependency[firrtl.transforms.InlineCastsTransform],
+      Dependency[firrtl.transforms.LegalizeClocksTransform],
+      Dependency[firrtl.transforms.FlattenRegUpdate]
+    )
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
 
@@ -51,32 +53,35 @@ object VerilogModulusCleanup extends Pass {
         case t => UnknownWidth
       }
 
-      def maxWidth(ws: Seq[Width]): Width = ws reduceLeft { (x,y) => (x,y) match {
-        case (IntWidth(x), IntWidth(y)) => IntWidth(x max y)
-        case (x, y) => UnknownWidth
-      }}
+      def maxWidth(ws: Seq[Width]): Width = ws.reduceLeft { (x, y) =>
+        (x, y) match {
+          case (IntWidth(x), IntWidth(y)) => IntWidth(x.max(y))
+          case (x, y)                     => UnknownWidth
+        }
+      }
 
       def verilogRemWidth(e: DoPrim)(tpe: Type): Type = {
         val newWidth = maxWidth(e.args.map(exp => getWidth(exp)))
-        tpe mapWidth (w => newWidth)
+        tpe.mapWidth(w => newWidth)
       }
 
       def removeRem(e: Expression): Expression = e match {
-        case e: DoPrim => e.op match {
-          case Rem =>
-            val name = namespace.newTemp
-            val newType = e mapType verilogRemWidth(e)
-            v += DefNode(get_info(s), name, e mapType verilogRemWidth(e))
-            val remRef = WRef(name, newType.tpe, kind(e), flow(e))
-            val remWidth = bitWidth(e.tpe)
-            DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe)
-          case _ => e
-        }
+        case e: DoPrim =>
+          e.op match {
+            case Rem =>
+              val name = namespace.newTemp
+              val newType = e.mapType(verilogRemWidth(e))
+              v += DefNode(get_info(s), name, e.mapType(verilogRemWidth(e)))
+              val remRef = WRef(name, newType.tpe, kind(e), flow(e))
+              val remWidth = bitWidth(e.tpe)
+              DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe)
+            case _ => e
+          }
         case _ => e
       }
 
-      s map removeRem match {
-        case x: Block => x map onStmt
+      s.map(removeRem) match {
+        case x: Block => x.map(onStmt)
         case EmptyStmt => EmptyStmt
         case x =>
           v += x
@@ -90,8 +95,8 @@ object VerilogModulusCleanup extends Pass {
   }
 
   def run(c: Circuit): Circuit = {
-    val modules = c.modules map {
-      case m: Module => onModule(m)
+    val modules = c.modules.map {
+      case m: Module    => onModule(m)
       case m: ExtModule => m
     }
     Circuit(c.info, modules, c.main)