diff options
| author | Adam Izraelevitz | 2017-03-23 16:16:24 -0700 |
|---|---|---|
| committer | GitHub | 2017-03-23 16:16:24 -0700 |
| commit | 67eb4e2de6166b8f1eb5190215640117b82e8c48 (patch) | |
| tree | 18cbaf901eff58262d833bf5bc0d75262c9ab57d /src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | |
| parent | 4cffd184397905eeb79e2df0913b4ded97dc8558 (diff) | |
Pass now subclasses Transform (#477)
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index b4df534f..330ca497 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -24,7 +24,6 @@ import scala.collection.mutable * to emit correct verilog without needing to add temporary nodes */ object VerilogModulusCleanup extends Pass { - def name = "Add temporary nodes with verilog widths for modulus" private def onModule(m: Module): Module = { val namespace = Namespace(m) |