diff options
| author | Schuyler Eldridge | 2020-04-22 19:55:32 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 19:55:32 -0400 |
| commit | 65360f886f9b92438d1b6fe609120b34ebb413cf (patch) | |
| tree | 073ebe73d43e652af1f71a08d34cc30a421c4dbb /src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | |
| parent | 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 (diff) | |
| parent | 184d40095179a9f49dd21e73e2c02b998bac5c00 (diff) | |
Merge pull request #1534 from freechipsproject/deprecate-transform-2
Trait-base Dependency API Migration
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index f47ddfbd..f063fccf 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -26,7 +26,7 @@ import scala.collection.mutable */ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], Dependency[firrtl.transforms.FixAddingNegativeLiterals], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], @@ -35,9 +35,9 @@ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { Dependency[firrtl.transforms.LegalizeClocksTransform], Dependency[firrtl.transforms.FlattenRegUpdate] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty private def onModule(m: Module): Module = { val namespace = Namespace(m) |