diff options
| author | Schuyler Eldridge | 2020-04-22 20:26:11 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 20:26:11 -0400 |
| commit | 404d419a42c33ce4a68eedce636c336adf7d53be (patch) | |
| tree | 607b55e30774227895c75b60fb8fd67845ed23a8 /src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | |
| parent | 65360f886f9b92438d1b6fe609120b34ebb413cf (diff) | |
| parent | ffa6958535292d636923739d9d77b566054e2208 (diff) | |
Merge pull request #1537 from freechipsproject/optionalPrerequisitesOf
Change `dependents` to `optionalPrerequisiteOf`
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index f063fccf..6debaf93 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -37,7 +37,7 @@ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty private def onModule(m: Module): Module = { val namespace = Namespace(m) |