diff options
| author | Schuyler Eldridge | 2019-07-17 14:08:33 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-09-16 17:12:51 -0400 |
| commit | a594ccef986c4567730fee729bdea9ed9aefed38 (patch) | |
| tree | 2512913e054ea7d56867f2c73912ff4be17f1e82 /src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
Rename gender to flow
The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index 330ca497..fdc81797 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -47,11 +47,11 @@ object VerilogModulusCleanup extends Pass { def removeRem(e: Expression): Expression = e match { case e: DoPrim => e.op match { - case Rem => + case Rem => val name = namespace.newTemp val newType = e mapType verilogRemWidth(e) v += DefNode(get_info(s), name, e mapType verilogRemWidth(e)) - val remRef = WRef(name, newType.tpe, kind(e), gender(e)) + val remRef = WRef(name, newType.tpe, kind(e), flow(e)) val remWidth = bitWidth(e.tpe) DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe) case _ => e |