diff options
| author | chick | 2016-09-23 16:40:08 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-25 14:39:44 -0700 |
| commit | 1f168585c80d5c96e41353d6275d99b34b967b23 (patch) | |
| tree | 44eee3d8e94cf41e2bd5094cff99ed58441cc7f4 /src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | |
| parent | 16286528ad957a7d62a9c1b18bd6335a3102ea5b (diff) | |
remove unnecessary blocks
example 1 s"${x}"
example 2 case blah => { ??? }
Diffstat (limited to 'src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala index 5b420591..675494b4 100644 --- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala +++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala @@ -78,7 +78,7 @@ object MemTransformUtils { for ((p, i) <- ports.zipWithIndex; f <- fields) { val newPort = createSubField(createRef(m.name), portType+i) val field = createSubField(newPort, f) - memPortMap(s"${m.name}.${p}.${f}") = field + memPortMap(s"${m.name}.$p.$f") = field } updateMemPortMap(m.readers, rFields, "R") updateMemPortMap(m.writers, wFields, "W") |