diff options
| author | chick | 2016-09-25 18:23:07 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-27 13:14:58 -0700 |
| commit | 3f8e1536ff2f4b5090cd2c074ada5d7a413d169f (patch) | |
| tree | c327771170e4438661b4d654e93960b92b31b023 /src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | |
| parent | 39f06c4cff41030e7802c7b371123e040d9c447b (diff) | |
remove unnecessary parentheses
Diffstat (limited to 'src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala index 675494b4..c3660fe0 100644 --- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala +++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala @@ -150,6 +150,6 @@ object UpdateDuplicateMemMacros extends Pass { map updateStmtRefs(memPortMap)) } - def run(c: Circuit) = c copy (modules = (c.modules map updateMemMods)) + def run(c: Circuit) = c copy (modules = c.modules map updateMemMods) } // TODO: Module namespace? |