diff options
| author | Chick Markley | 2016-10-11 15:53:40 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2016-10-11 15:53:40 -0700 |
| commit | 2848d87721df110d0425114283cb5fa7e6c2ee03 (patch) | |
| tree | d76dd381fb77d63b8509a69063ace380f3209f33 /src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | |
| parent | 515f29f5993abb399db43b04e9a63c0fdf347ecc (diff) | |
Scala style cleanup take 5 (#324)
* working through variable shrouding
* working through variable shrouding
* working through variable shadowing
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* Fixes suggested by Adam
Diffstat (limited to 'src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala index c3660fe0..2e6c3338 100644 --- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala +++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala @@ -115,7 +115,7 @@ object MemTransformUtils { def updateStmtRefs(s: Statement): Statement = s map updateStmtRefs map updateRef match { case c: Connect if hasEmptyExpr(c) => EmptyStmt - case s => s + case sx => sx } updateStmtRefs(s) @@ -140,7 +140,7 @@ object UpdateDuplicateMemMacros extends Pass { case Some(proto) => updatedMem copy (info = appendInfo(updatedMem.info, "ref" -> proto.name)) } - case s => s map updateMemStmts(uniqueMems, memPortMap) + case sx => sx map updateMemStmts(uniqueMems, memPortMap) } def updateMemMods(m: DefModule) = { |