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authorchick2020-08-14 19:47:53 -0700
committerJack Koenig2020-08-14 19:47:53 -0700
commit6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (patch)
tree2ed103ee80b0fba613c88a66af854ae9952610ce /src/main/scala/firrtl/passes/ToWorkingIR.scala
parentb516293f703c4de86397862fee1897aded2ae140 (diff)
All of src/ formatted with scalafmt
Diffstat (limited to 'src/main/scala/firrtl/passes/ToWorkingIR.scala')
-rw-r--r--src/main/scala/firrtl/passes/ToWorkingIR.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ToWorkingIR.scala b/src/main/scala/firrtl/passes/ToWorkingIR.scala
index c271302a..03faaf3c 100644
--- a/src/main/scala/firrtl/passes/ToWorkingIR.scala
+++ b/src/main/scala/firrtl/passes/ToWorkingIR.scala
@@ -6,5 +6,5 @@ import firrtl.Transform
object ToWorkingIR extends Pass {
override def prerequisites = firrtl.stage.Forms.MinimalHighForm
override def invalidates(a: Transform) = false
- def run(c:Circuit): Circuit = c
+ def run(c: Circuit): Circuit = c
}