diff options
| author | Schuyler Eldridge | 2020-04-22 19:55:32 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 19:55:32 -0400 |
| commit | 65360f886f9b92438d1b6fe609120b34ebb413cf (patch) | |
| tree | 073ebe73d43e652af1f71a08d34cc30a421c4dbb /src/main/scala/firrtl/passes/SplitExpressions.scala | |
| parent | 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 (diff) | |
| parent | 184d40095179a9f49dd21e73e2c02b998bac5c00 (diff) | |
Merge pull request #1534 from freechipsproject/deprecate-transform-2
Trait-base Dependency API Migration
Diffstat (limited to 'src/main/scala/firrtl/passes/SplitExpressions.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/SplitExpressions.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index 43d0ed34..808f9f0d 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -16,11 +16,11 @@ import scala.collection.mutable // and named intermediate nodes object SplitExpressions extends Pass with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowForm ++ + override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency(firrtl.passes.memlib.VerilogMemDelays) ) - override val dependents = + override def dependents = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) |