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| author | Adam Izraelevitz | 2016-09-25 20:35:09 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-25 20:35:09 -0700 |
| commit | e54fb610c6bf0a7fe5c9c0f0e0b3acbb3728cfd0 (patch) | |
| tree | 7c186c96c782f488a9ceea21abb3f60594bf98c7 /src/main/scala/firrtl/passes/Resolves.scala | |
| parent | 7c4fa71a062f0c18a3af13c9e8853fdec2818da9 (diff) | |
Spec features added: AnalogType and Attach (#295)
* Spec features added: AnalogType and Attach
AnalogType(width: Width):
- Concrete syntax:
wire x: AnalogType<10>
- New groundtype, very restricted in use cases.
- Can only declare ports and wires with Analog type
- Analog types are never equivalent, thus if x and y have Analog
types: x <= y is never legal.
Attach(info: Info, source: Expression, exprs: Seq[Expression]):
- Concrete syntax:
attach x to (y, z)
- New statement
- Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
- Exprs must have an Analog type reference an instance port
- Source and exprs must have identical widths
Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.
* Fixed bug where invalidated ports aren't handled
* Bugfix for VerilogPrep
Intermediate wires for invalidated instance ports were not invalidated
* Bugfix: calling create_exp with name/tpe
Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals
* Addressed donggyukim's style comments
* Reworked pass to only allow analog types in attach
Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)
* Fixup bugs from pulling in new changes from master
* comments for type eqs and small style fixes
Diffstat (limited to 'src/main/scala/firrtl/passes/Resolves.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Resolves.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala index 616e30f3..49df9ba6 100644 --- a/src/main/scala/firrtl/passes/Resolves.scala +++ b/src/main/scala/firrtl/passes/Resolves.scala @@ -87,6 +87,7 @@ object ResolveGenders extends Pass { } def resolve_s(s: Statement): Statement = s match { + //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive... case IsInvalid(info, expr) => IsInvalid(info, resolve_e(FEMALE)(expr)) case Connect(info, loc, expr) => |