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| author | chick | 2016-09-25 18:23:07 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-27 13:14:58 -0700 |
| commit | 3f8e1536ff2f4b5090cd2c074ada5d7a413d169f (patch) | |
| tree | c327771170e4438661b4d654e93960b92b31b023 /src/main/scala/firrtl/passes/ReplSeqMem.scala | |
| parent | 39f06c4cff41030e7802c7b371123e040d9c447b (diff) | |
remove unnecessary parentheses
Diffstat (limited to 'src/main/scala/firrtl/passes/ReplSeqMem.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/ReplSeqMem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala index 3b51d73f..62546a84 100644 --- a/src/main/scala/firrtl/passes/ReplSeqMem.scala +++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala @@ -88,7 +88,7 @@ Optional Arguments: error("No circuit name specified for ReplSeqMem!" + usage) ) val target = CircuitName(passCircuit) - def duplicate(n: Named) = this copy (t = (t replace (s"-c:$passCircuit", s"-c:${n.name}"))) + def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}")) } class ReplSeqMem(transID: TransID) extends Transform with SimpleRun { |