diff options
| author | Donggyu | 2016-09-25 14:56:46 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-25 14:56:46 -0700 |
| commit | 744ea401553cabfb31c7cc32aecfd8ca2764d1b8 (patch) | |
| tree | 628d4ce1d4bebc228fadd5a74365019f0dc5c62b /src/main/scala/firrtl/passes/RemoveValidIf.scala | |
| parent | bd1a3ae2d1130fbfb51ad4ef88349364c931680d (diff) | |
| parent | 2e553ec9859c369938ed035c83040dd80877f893 (diff) | |
Merge pull request #316 from ucb-bar/style-cleanup-take-3
Style cleanup take 3
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveValidIf.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index e0a4b621..3b4daee2 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -23,5 +23,5 @@ object RemoveValidIf extends Pass { } } - def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main) + def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule), c.main) } |