diff options
| author | Schuyler Eldridge | 2019-02-22 17:45:26 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-02-25 00:16:25 -0500 |
| commit | 5decb4079814be1fef10a02bf5518ec4e29f37dd (patch) | |
| tree | 8a827aa0830adaa4dde8fef8185987a64938ffc1 /src/main/scala/firrtl/passes/RemoveValidIf.scala | |
| parent | 5608aa8f42c1d69b59bee158d14fc6cef9b19a47 (diff) | |
Fix almost all Scaladoc warnings
This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveValidIf.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index 5338a911..b9f13139 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -7,7 +7,7 @@ import firrtl.ir._ import Utils.throwInternalError import WrappedExpression.weq -/** Remove ValidIf and replace IsInvalid with a connection to zero */ +/** Remove [[firrtl.ir.ValidIf ValidIf]] and replace [[firrtl.ir.IsInvalid IsInvalid]] with a connection to zero */ object RemoveValidIf extends Pass { val UIntZero = Utils.zero @@ -15,8 +15,8 @@ object RemoveValidIf extends Pass { val ClockZero = DoPrim(PrimOps.AsClock, Seq(UIntZero), Seq.empty, ClockType) val FixedZero = FixedLiteral(BigInt(0), IntWidth(1), IntWidth(0)) - /** Returns an [[Expression]] equal to zero for a given [[GroundType]] - * @note Accepts [[Type]] but dyanmically expects [[GroundType]] + /** Returns an [[firrtl.ir.Expression Expression]] equal to zero for a given [[firrtl.ir.GroundType GroundType]] + * @note Accepts [[firrtl.ir.Type Type]] but dyanmically expects [[firrtl.ir.GroundType GroundType]] */ def getGroundZero(tpe: Type): Expression = tpe match { case _: UIntType => UIntZero |