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authorSchuyler Eldridge2020-06-19 01:11:15 -0400
committerSchuyler Eldridge2020-06-22 19:00:20 -0400
commitd66ff2357e59113ecf48c7d257edff429c4266e0 (patch)
tree30f5d068ea78caf172008f900e3d4fde7e20f6b0 /src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
parent2d1e074a67483c136d5f0ed86e8ecf1b8505bc10 (diff)
Convert PreservesAll to explicit invalidates=false
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
-rw-r--r--src/main/scala/firrtl/passes/RemoveCHIRRTL.scala6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 67181f2b..8ba783ca 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -8,18 +8,20 @@ import firrtl._
import firrtl.ir._
import firrtl.Utils._
import firrtl.Mappers._
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
case class MPort(name: String, clk: Expression)
case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort])
case class DataRef(exp: Expression, male: String, female: String, mask: String, rdwrite: Boolean)
-object RemoveCHIRRTL extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
override def prerequisites = firrtl.stage.Forms.ChirrtlForm ++
Seq( Dependency(passes.CInferTypes),
Dependency(passes.CInferMDir) )
+ override def invalidates(a: Transform) = false
+
val ut = UnknownType
type MPortMap = collection.mutable.LinkedHashMap[String, MPorts]
type SeqMemSet = collection.mutable.HashSet[String]