diff options
| author | Schuyler Eldridge | 2019-12-17 18:29:47 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-11 14:01:31 -0400 |
| commit | abf226471249a1cbb8de33d0c4bc8526f9aafa70 (patch) | |
| tree | 0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | |
| parent | 646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff) | |
Migrate to DependencyAPI
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index 921ec3c7..05dd8bd9 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -8,12 +8,18 @@ import firrtl._ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ +import firrtl.options.{Dependency, PreservesAll} case class MPort(name: String, clk: Expression) case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) case class DataRef(exp: Expression, male: String, female: String, mask: String, rdwrite: Boolean) -object RemoveCHIRRTL extends Transform { +object RemoveCHIRRTL extends Transform with PreservesAll[Transform] { + + override val prerequisites = firrtl.stage.Forms.ChirrtlForm ++ + Seq( Dependency(passes.CInferTypes), + Dependency(passes.CInferMDir) ) + def inputForm: CircuitForm = UnknownForm def outputForm: CircuitForm = UnknownForm val ut = UnknownType |