diff options
| author | Albert Magyar | 2019-09-11 18:16:20 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-09-30 16:22:01 -0700 |
| commit | a10084fbba0ba88a1f0517b826ef8de44d8760d1 (patch) | |
| tree | 8a1ac0098409dbb95a45d3b7107a4f6d59d8e166 /src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | |
| parent | 4ca2b859473e0a88723463eac2821cfbd3249c43 (diff) | |
Improve read-under-write parameter support
* Make the read-under-write (RUW) parameter typesafe
* Add RUW support to the FIRRTL proto and CHIRRTL grammar
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index d0498cf0..5e93b3b9 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -99,7 +99,7 @@ object RemoveCHIRRTL extends Transform { set_enable(rws, "en") ++ set_write(rws, "wdata", "wmask") val mem = DefMemory(sx.info, sx.name, sx.tpe, sx.size, 1, if (sx.seq) 1 else 0, - rds map (_.name), wrs map (_.name), rws map (_.name)) + rds map (_.name), wrs map (_.name), rws map (_.name), sx.readUnderWrite) Block(mem +: stmts) case sx: CDefMPort => types.get(sx.mem) match { |