diff options
| author | Adam Izraelevitz | 2018-02-22 17:25:55 -0800 |
|---|---|---|
| committer | GitHub | 2018-02-22 17:25:55 -0800 |
| commit | 46b78943a726e4c9bf85ffb25a2ccf926b10dda7 (patch) | |
| tree | 39f9363400fdd39e2e55f3dc8c5221461941edec /src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | |
| parent | 65bbf155003a86cd836f7ff4a2def6af91794780 (diff) | |
Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, but not Emitter. (#717)
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index c841dc32..6b3508a6 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -4,11 +4,11 @@ package firrtl.passes // Datastructures import scala.collection.mutable.ArrayBuffer - import firrtl._ import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ +import firrtl.PrimOps.AsClock case class MPort(name: String, clk: Expression) case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) |