Merge branch 'master' into top-wiring-aggregates

1 files changed, 5 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index cc69be6f..5a9a60f8 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -103,7 +103,11 @@ object RemoveCHIRRTL extends Transform {
                   rds map (_.name), wrs map (_.name), rws map (_.name))
       Block(mem +: stmts)
     case sx: CDefMPort =>
-      types(sx.name) = types(sx.mem)
+      types.get(sx.mem) match {
+        case Some(mem) => types(sx.name) = mem
+        case None =>
+          throw new PassException(s"Undefined memory ${sx.mem} referenced by mport ${sx.name}")
+      }
       val addrs = ArrayBuffer[String]()
       val clks = ArrayBuffer[String]()
       val ens = ArrayBuffer[String]()