diff options
| author | Andrew Waterman | 2016-09-13 20:54:20 -0700 |
|---|---|---|
| committer | Donggyu | 2016-09-13 20:54:20 -0700 |
| commit | 8fc37582267b2319e5fa25818fcd1346d8e180ae (patch) | |
| tree | 2a9e2ae060cb7be6b417408d3cbd3e282cc690bc /src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | |
| parent | 36c19ed40bec120ef38aefa7e2c875c5e21bf048 (diff) | |
Fix a lurking width-inference bug; improve adjacent style (#298)
ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)).
I noticed this because of #297.
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveCHIRRTL.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index b71c0dc3..6eeb6e96 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -88,7 +88,7 @@ object RemoveCHIRRTL extends Pass { refs: DataRefMap, raddrs: AddrMap)(s: Statement): Statement = s match { case (s: CDefMemory) => types(s.name) = s.tpe - val taddr = UIntType(IntWidth(math.max(1, ceil_log2(s.size)))) + val taddr = UIntType(IntWidth(1 max ceilLog2(s.size))) val tdata = s.tpe def set_poison(vec: Seq[MPort], addr: String) = vec flatMap (r => Seq( IsInvalid(s.info, SubField(SubField(Reference(s.name, ut), r.name, ut), addr, taddr)), |