diff options
| author | Schuyler Eldridge | 2019-12-17 18:29:47 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-11 14:01:31 -0400 |
| commit | abf226471249a1cbb8de33d0c4bc8526f9aafa70 (patch) | |
| tree | 0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/passes/RemoveAccesses.scala | |
| parent | 646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff) | |
Migrate to DependencyAPI
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveAccesses.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveAccesses.scala | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala index 1c2dc096..ac5d8a4e 100644 --- a/src/main/scala/firrtl/passes/RemoveAccesses.scala +++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala @@ -2,18 +2,30 @@ package firrtl.passes -import firrtl.{WRef, WSubAccess, WSubIndex, WSubField, Namespace} +import firrtl.{Namespace, Transform, WRef, WSubAccess, WSubIndex, WSubField} import firrtl.PrimOps.{And, Eq} import firrtl.ir._ import firrtl.Mappers._ import firrtl.Utils._ import firrtl.WrappedExpression._ -import scala.collection.mutable +import firrtl.options.Dependency +import scala.collection.mutable /** Removes all [[firrtl.WSubAccess]] from circuit */ -class RemoveAccesses extends Pass { +object RemoveAccesses extends Pass { + + override val prerequisites = + Seq( Dependency(PullMuxes), + Dependency(ReplaceAccesses), + Dependency(ExpandConnects) ) ++ firrtl.stage.Forms.Deduped + + override def invalidates(a: Transform): Boolean = a match { + case Uniquify => true + case _ => false + } + private def AND(e1: Expression, e2: Expression) = if(e1 == one) e2 else if(e2 == one) e1 @@ -166,14 +178,3 @@ class RemoveAccesses extends Pass { }) } } - -object RemoveAccesses extends Pass { - def apply: Pass = { - new RemoveAccesses() - } - - def run(c: Circuit): Circuit = { - val t = new RemoveAccesses - t.run(c) - } -} |
