Pass now subclasses Transform (#477)

1 files changed, 16 insertions, 10 deletions

diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index c595727e..68f278a9 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -12,9 +12,23 @@ import firrtl.PrimOps._
 
 import scala.collection.mutable
 
-trait Pass extends LazyLogging {
-  def name: String
+/** [[Pass]] is simple transform that is generally part of a larger [[Transform]]
+  * Has an [[UnknownForm]], because larger [[Transform]] should specify form
+  */
+trait Pass extends Transform {
+  def inputForm: CircuitForm = UnknownForm
+  def outputForm: CircuitForm = UnknownForm
   def run(c: Circuit): Circuit
+  def execute(state: CircuitState): CircuitState = {
+    val result = (state.form, inputForm) match {
+      case (_, UnknownForm) => run(state.circuit)
+      case (UnknownForm, _) => run(state.circuit)
+      case (x, y) if x > y =>
+        error(s"[$name]: Input form must be lower or equal to $inputForm. Got ${state.form}")
+      case _ => run(state.circuit)
+    }
+    CircuitState(result, outputForm, state.annotations, state.renames)
+  }
 }
 
 // Error handling
@@ -34,8 +48,6 @@ class Errors {
 
 // These should be distributed into separate files
 object ToWorkingIR extends Pass {
-  def name = "Working IR"
-
   def toExp(e: Expression): Expression = e map toExp match {
     case ex: Reference => WRef(ex.name, ex.tpe, NodeKind, UNKNOWNGENDER)
     case ex: SubField => WSubField(ex.expr, ex.name, ex.tpe, UNKNOWNGENDER)
@@ -54,7 +66,6 @@ object ToWorkingIR extends Pass {
 }
 
 object PullMuxes extends Pass {
-   def name = "Pull Muxes"
    def run(c: Circuit): Circuit = {
      def pull_muxes_e(e: Expression): Expression = e map pull_muxes_e match {
        case ex: WSubField => ex.exp match {
@@ -93,7 +104,6 @@ object PullMuxes extends Pass {
 }
 
 object ExpandConnects extends Pass {
-  def name = "Expand Connects"
   def run(c: Circuit): Circuit = {
     def expand_connects(m: Module): Module = {
       val genders = collection.mutable.LinkedHashMap[String,Gender]()
@@ -171,7 +181,6 @@ object ExpandConnects extends Pass {
 // Replace shr by amount >= arg width with 0 for UInts and MSB for SInts
 // TODO replace UInt with zero-width wire instead
 object Legalize extends Pass {
-  def name = "Legalize"
   private def legalizeShiftRight(e: DoPrim): Expression = {
     require(e.op == Shr)
     val amount = e.consts.head.toInt
@@ -244,7 +253,6 @@ object Legalize extends Pass {
 }
 
 object VerilogWrap extends Pass {
-  def name = "Verilog Wrap"
   def vWrapE(e: Expression): Expression = e map vWrapE match {
     case e: DoPrim => e.op match {
       case Tail => e.args.head match {
@@ -271,7 +279,6 @@ object VerilogWrap extends Pass {
 }
 
 object VerilogRename extends Pass {
-  def name = "Verilog Rename"
   def verilogRenameN(n: String): String =
     if (v_keywords(n)) "%s$".format(n) else n
 
@@ -301,7 +308,6 @@ object VerilogRename extends Pass {
   * @note The result of this pass is NOT legal Firrtl
   */
 object VerilogPrep extends Pass {
-  def name = "Verilog Prep"
 
   type AttachSourceMap = Map[WrappedExpression, Expression]