diff options
| author | Angie Wang | 2017-01-27 16:00:24 -0800 |
|---|---|---|
| committer | GitHub | 2017-01-27 16:00:24 -0800 |
| commit | 7240b4f6590413d4c4fd4e0324bbd440ae783388 (patch) | |
| tree | 2a19561f6302f22b96e421b949c67b36e0d1d3d2 /src/main/scala/firrtl/passes/Passes.scala | |
| parent | 91570ec8d7ab6bede24eb8da4a7e005f00ac076f (diff) | |
Fix signed types (#422)
* type conversions between sint/fixed and uint added at memory interfaces for replseqmem
* turns out asFixed requires bp as constant in PrimOps (really should be documented)
* fixed legalizeconnects to handle FixedPt
* added tests for replseqmem failure with signed types
Diffstat (limited to 'src/main/scala/firrtl/passes/Passes.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 87458a2b..0e91c642 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -210,7 +210,7 @@ object Legalize extends Pass { val expr = t match { case UIntType(_) => bits case SIntType(_) => DoPrim(AsSInt, Seq(bits), Seq(), SIntType(IntWidth(w))) - //case FixedType(width, point) => FixedType(width, point) + case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(bits), Seq(p), t) } Connect(c.info, c.loc, expr) } |
