diff options
| author | Angie Wang | 2016-08-17 13:34:14 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-08-17 13:34:14 -0700 |
| commit | 5db4abebb7ceb5939a9efca158d78e3dc0e32c44 (patch) | |
| tree | fd8c5b5231a8f097962a5c7c95a079b79e8e9d4f /src/main/scala/firrtl/passes/Passes.scala | |
| parent | 673d7c6e11c80d7439a416b4dcb206e6777d89cf (diff) | |
Change RW port names (#236)
* Updated FIRRTL spec + related code for readwrite ports.
(write) data -> wdata & mask -> wmask for clarity
* Also removed simple.fir that snuck into master branch.
Diffstat (limited to 'src/main/scala/firrtl/passes/Passes.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index a8580988..1b6c76f4 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -1147,7 +1147,7 @@ object RemoveCHIRRTL extends Pass { set_poison(rws,"addr") set_wmode(rws,"wmode") set_enable(rws,"en") - set_write(rws,"data","mask") + set_write(rws,"wdata","wmask") val read_l = if (s.seq) 1 else 0 val mem = DefMemory(s.info,s.name,s.tpe,s.size,1,read_l,rds.map(_.name),wrs.map(_.name),rws.map(_.name)) Block(Seq(mem,Block(stmts))) @@ -1160,11 +1160,11 @@ object RemoveCHIRRTL extends Pass { val masks = ArrayBuffer[String]() s.direction match { case MReadWrite => { - repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"rdata","data","mask",true) + repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"rdata","wdata","wmask",true) addrs += "addr" clks += "clk" ens += "en" - masks += "mask" + masks += "wmask" } case MWrite => { repl(s.name) = DataRef(SubField(Reference(s.mem,ut),s.name,ut),"data","data","mask",false) |