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| author | Donggyu | 2016-09-13 17:36:50 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-13 17:36:50 -0700 |
| commit | 7c38199ce7a5d9dd7e27ffbb9b2b2770b972ed94 (patch) | |
| tree | 2f525cb9ea765b3b3031eef94532a3880f3f55e3 /src/main/scala/firrtl/passes/Inline.scala | |
| parent | 1bb9597a01e77d9a1ece479caf13cf6c3f6229d5 (diff) | |
use case object for Kind (#267)
use case object for Kind
Diffstat (limited to 'src/main/scala/firrtl/passes/Inline.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Inline.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index 43c0ef1e..12dfb497 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -106,7 +106,7 @@ class InlineInstances (transID: TransID) extends Transform { if (inlinedInstances.contains(ref)) { val newName = ref + inlineDelim + field set(ComponentName(ref, ModuleName(m.name, cname)), Seq.empty) - WRef(newName, tpe, WireKind(), gen) + WRef(newName, tpe, WireKind, gen) } else e } |