diff options
| author | Chick Markley | 2016-10-11 15:53:40 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2016-10-11 15:53:40 -0700 |
| commit | 2848d87721df110d0425114283cb5fa7e6c2ee03 (patch) | |
| tree | d76dd381fb77d63b8509a69063ace380f3209f33 /src/main/scala/firrtl/passes/Inline.scala | |
| parent | 515f29f5993abb399db43b04e9a63c0fdf347ecc (diff) | |
Scala style cleanup take 5 (#324)
* working through variable shrouding
* working through variable shrouding
* working through variable shadowing
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* Fixes suggested by Adam
Diffstat (limited to 'src/main/scala/firrtl/passes/Inline.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Inline.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index e2a69751..5c80baff 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -108,7 +108,7 @@ class InlineInstances (transID: TransID) extends Transform { WRef(newName, tpe, WireKind, gen) } else e - case e => e map onExp + case ex => ex map onExp } // Recursive. Inlines tagged instances def onStmt(s: Statement): Statement = s match { @@ -123,7 +123,7 @@ class InlineInstances (transID: TransID) extends Transform { def renameExp(e: Expression): Expression = { e map renameExp match { case WRef(name, tpe, kind, gen) => WRef(rename(name), tpe, kind, gen) - case e => e + case ex => ex } } s map rename map renameStmt map renameExp @@ -151,16 +151,16 @@ class InlineInstances (transID: TransID) extends Transform { stmts += renameStmt(instInModule.body) Block(stmts.toSeq) } else s - case s => s map onExp map onStmt + case sx => sx map onExp map onStmt } m match { case Module(info, name, ports, body) => val mx = Module(info, name, ports, onStmt(body)) inlinedModules(name) = mx mx - case m: ExtModule => - inlinedModules(m.name) = m - m + case mx: ExtModule => + inlinedModules(mx.name) = mx + mx } } |