Add fixed point type (#322)

* WIP: Adding FixedType to Firrtl proper

Got simple example running through width inference
Checks should be ok
Need to look into FixedLiteral more

* Added simple test for fixed types

* Added asFixedPoint to primops

* Added tail case for FixedType

* Added ConvertFixedToSInt.scala

Added pass to MiddleToLowerFirrtl transform

* Replace AsFixedType with AsSInt in fixed removal

* Bugfix: constant from asFixed not deleted

* Added unit test for bulk connect

* Fixed partial connect bug #241

* Fixed missing case for FixedPoint in legalizeConnect

* Add FixedMathSpec that demonstrates some problems with FixedPointMath

* Fixed test and ConvertToSInt to pass.

Negative binary points not easily supported, needs much more time to
implement.

* Refactored checking neg widths

Make checking for negative binary points easier

* Added tests for inferring many FixedType ops

shl, shr, cat, bits, head, tail, setbp, shiftbp

* Handle bpshl, bpshr, bpset in ConvertFixedToSInt

Changed name from shiftbp -> bpshl, bpshr
Change name from setbp -> bpset
Added more tests

* Added set binary point test that fails

* Added simple test for zero binary point

* gitignore fixes for antlr intermediate dir and intellij dir

* removed unused imports
retool the fixed point with zero binary point test

* simplified example of inability to set binary point to zero

* Temporary fix for zero-width binary point

This fix allows for all widths to be zero, but since this is a feature I
am working on next, I'm not going to bother with a more stringent check.

* change version for dsp tools

* Removed extra temporary file

* Fixed merge bug

* Fixed another merge bug

* Removed commented out/unrelated files

* Removed snake case

1 files changed, 30 insertions, 18 deletions

diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 8fd5eef1..ac786386 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -200,14 +200,19 @@ object InferWidths extends Pass {
   def run (c: Circuit): Circuit = {
     val v = ArrayBuffer[WGeq]()
 
-    def get_constraints_t(t1: Type, t2: Type, f: Orientation): Seq[WGeq] = (t1,t2) match {
+    def get_constraints_t(t1: Type, t2: Type): Seq[WGeq] = (t1,t2) match {
       case (t1: UIntType, t2: UIntType) => Seq(WGeq(t1.width, t2.width))
       case (t1: SIntType, t2: SIntType) => Seq(WGeq(t1.width, t2.width))
+      case (ClockType, ClockType) => Nil
+      case (FixedType(w1, p1), FixedType(w2, p2)) => Seq(WGeq(w1,w2), WGeq(p1,p2))
       case (t1: BundleType, t2: BundleType) =>
         (t1.fields zip t2.fields foldLeft Seq[WGeq]()){case (res, (f1, f2)) =>
-          res ++ get_constraints_t(f1.tpe, f2.tpe, times(f1.flip, f))
+          res ++ (f1.flip match {
+            case Default => get_constraints_t(f1.tpe, f2.tpe)
+            case Flip => get_constraints_t(f2.tpe, f1.tpe)
+          })
         }
-      case (t1: VectorType, t2: VectorType) => get_constraints_t(t1.tpe, t2.tpe, f)
+      case (t1: VectorType, t2: VectorType) => get_constraints_t(t1.tpe, t2.tpe)
     }
 
     def get_constraints_e(e: Expression): Expression = {
@@ -221,38 +226,44 @@ object InferWidths extends Pass {
       e map get_constraints_e
     }
 
+    def get_constraints_declared_type (t: Type): Type = t match {
+      case FixedType(_, p) => 
+        v += WGeq(p,IntWidth(0))
+        t
+      case _ => t map get_constraints_declared_type
+    }
+
     def get_constraints_s(s: Statement): Statement = {
-      s match {
+      s map get_constraints_declared_type match {
         case (s: Connect) =>
           val n = get_size(s.loc.tpe)
           val locs = create_exps(s.loc)
           val exps = create_exps(s.expr)
-          v ++= ((locs zip exps).zipWithIndex map {case ((locx, expx), i) =>
+          v ++= ((locs zip exps).zipWithIndex flatMap {case ((locx, expx), i) =>
             get_flip(s.loc.tpe, i, Default) match {
-              case Default => WGeq(getWidth(locx), getWidth(expx))
-              case Flip => WGeq(getWidth(expx), getWidth(locx))
+              case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx))
+              case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx))
             }
           })
         case (s: PartialConnect) =>
           val ls = get_valid_points(s.loc.tpe, s.expr.tpe, Default, Default)
           val locs = create_exps(s.loc)
           val exps = create_exps(s.expr)
-          v ++= (ls map {case (x, y) =>
+          v ++= (ls flatMap {case (x, y) =>
             val locx = locs(x)
             val expx = exps(y)
             get_flip(s.loc.tpe, x, Default) match {
-              case Default => WGeq(getWidth(locx), getWidth(expx))
-              case Flip => WGeq(getWidth(expx), getWidth(locx))
+              case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx))
+              case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx))
             }
           })
-        case (s:DefRegister) => v ++= (Seq(
-           WGeq(getWidth(s.reset), IntWidth(1)),
-           WGeq(IntWidth(1), getWidth(s.reset))
-        ) ++ get_constraints_t(s.tpe, s.init.tpe, Default))
-        case (s:Conditionally) => v ++= Seq(
-           WGeq(getWidth(s.pred), IntWidth(1)),
-           WGeq(IntWidth(1), getWidth(s.pred))
-        )
+        case (s: DefRegister) => v ++= (
+           get_constraints_t(s.reset.tpe, UIntType(IntWidth(1))) ++
+           get_constraints_t(UIntType(IntWidth(1)), s.reset.tpe) ++ 
+           get_constraints_t(s.tpe, s.init.tpe))
+        case (s:Conditionally) => v ++= 
+           get_constraints_t(s.pred.tpe, UIntType(IntWidth(1))) ++
+           get_constraints_t(UIntType(IntWidth(1)), s.pred.tpe)
         case (s: Attach) =>
           v += WGeq(getWidth(s.source), MaxWidth(s.exprs map (e => getWidth(e.tpe))))
         case _ =>
@@ -261,6 +272,7 @@ object InferWidths extends Pass {
     }
 
     c.modules foreach (_ map get_constraints_s)
+    c.modules foreach (_.ports foreach {p => get_constraints_declared_type(p.tpe)})
 
     //println("======== ALL CONSTRAINTS ========")
     //for(x <- v) println(x)