diff options
| author | Kamyar Mohajerani | 2016-07-21 23:40:34 +0430 |
|---|---|---|
| committer | Jack Koenig | 2016-07-21 12:10:34 -0700 |
| commit | ab340febdc7a5418da945f9b79624d36e66e26db (patch) | |
| tree | 04e4aef30081fdd419281d69be4b141fd49b4b1f /src/main/scala/firrtl/passes/ExpandWhens.scala | |
| parent | b7de40e23161a7346fea90576f07b5c200c2675b (diff) | |
Indentation support for the ANTLR parser (as discussed in #192) (#194)
Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
Diffstat (limited to 'src/main/scala/firrtl/passes/ExpandWhens.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index b6e090f4..6df7664b 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -73,12 +73,12 @@ object ExpandWhens extends Pass { } private def squashEmpty(s: Statement): Statement = { s map squashEmpty match { - case Begin(stmts) => + case Block(stmts) => val newStmts = stmts filter (_ != EmptyStmt) newStmts.size match { case 0 => EmptyStmt case 1 => newStmts.head - case _ => Begin(newStmts) + case _ => Block(newStmts) } case s => s } @@ -157,7 +157,7 @@ object ExpandWhens extends Pass { memos += memoNode netlist(lvalue) = memoExpr } - Begin(Seq(conseqStmt, altStmt) ++ memos) + Block(Seq(conseqStmt, altStmt) ++ memos) case s: Print => if(weq(p, one)) { @@ -191,7 +191,7 @@ object ExpandWhens extends Pass { case m: ExtModule => m case m: Module => val (netlist, simlist, bodyx) = expandWhens(m) - val newBody = Begin(Seq(bodyx map squashEmpty) ++ expandNetlist(netlist) ++ simlist) + val newBody = Block(Seq(bodyx map squashEmpty) ++ expandNetlist(netlist) ++ simlist) Module(m.info, m.name, m.ports, newBody) } } |
