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authorJack2016-05-09 16:04:52 -0700
committerJack Koenig2016-06-10 16:31:50 -0700
commit2bf1c9e84b7affb82fd08484285250ce8f7b6f26 (patch)
tree7e2276fc5405029ec5acd75b81c985e3d61989b5 /src/main/scala/firrtl/passes/DeadCodeElimination.scala
parent83f53a3a0cdcfc7537e923b827ab820205025d45 (diff)
API Cleanup - Module
trait Module -> abstract class DefModule InModule -> Module (match concrete syntax) ExModule -> ExtModule (match concrete syntax) Add simple scaladoc for each one
Diffstat (limited to 'src/main/scala/firrtl/passes/DeadCodeElimination.scala')
-rw-r--r--src/main/scala/firrtl/passes/DeadCodeElimination.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/DeadCodeElimination.scala b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
index cb772556..cdff1639 100644
--- a/src/main/scala/firrtl/passes/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
@@ -76,8 +76,8 @@ object DeadCodeElimination extends Pass {
def run(c: Circuit): Circuit = {
val modulesx = c.modules.map {
- case m: ExModule => m
- case m: InModule => InModule(m.info, m.name, m.ports, dce(m.body))
+ case m: ExtModule => m
+ case m: Module => Module(m.info, m.name, m.ports, dce(m.body))
}
Circuit(c.info, modulesx, c.main)
}