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authorKevin Laeufer2021-08-02 13:46:29 -0700
committerGitHub2021-08-02 20:46:29 +0000
commite04f1e7f303920ac1d1f865450d0e280aafb58b3 (patch)
tree73f26cd236ac8069d9c4877a3c42457d65d477fe /src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
parentff1cd28202fb423956a6803a889c3632487d8872 (diff)
add emitter for optimized low firrtl (#2304)
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala')
-rw-r--r--src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index e70346d4..70da011e 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -9,15 +9,7 @@ import firrtl.options.Dependency
object CommonSubexpressionElimination extends Pass {
- override def prerequisites = firrtl.stage.Forms.LowForm ++
- Seq(
- Dependency(firrtl.passes.RemoveValidIf),
- Dependency[firrtl.transforms.ConstantPropagation],
- Dependency(firrtl.passes.memlib.VerilogMemDelays),
- Dependency(firrtl.passes.SplitExpressions),
- Dependency[firrtl.transforms.CombineCats]
- )
-
+ override def prerequisites = firrtl.stage.Forms.LowForm
override def optionalPrerequisiteOf =
Seq(Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter])