All of src/ formatted with scalafmt

1 files changed, 20 insertions, 17 deletions

diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index 544f90a6..55a9c53a 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -10,15 +10,16 @@ import firrtl.options.Dependency
 object CommonSubexpressionElimination extends Pass {
 
   override def prerequisites = firrtl.stage.Forms.LowForm ++
-    Seq( Dependency(firrtl.passes.RemoveValidIf),
-         Dependency[firrtl.transforms.ConstantPropagation],
-         Dependency(firrtl.passes.memlib.VerilogMemDelays),
-         Dependency(firrtl.passes.SplitExpressions),
-         Dependency[firrtl.transforms.CombineCats] )
+    Seq(
+      Dependency(firrtl.passes.RemoveValidIf),
+      Dependency[firrtl.transforms.ConstantPropagation],
+      Dependency(firrtl.passes.memlib.VerilogMemDelays),
+      Dependency(firrtl.passes.SplitExpressions),
+      Dependency[firrtl.transforms.CombineCats]
+    )
 
   override def optionalPrerequisiteOf =
-    Seq( Dependency[SystemVerilogEmitter],
-         Dependency[VerilogEmitter] )
+    Seq(Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter])
 
   override def invalidates(a: Transform) = false
 
@@ -27,24 +28,26 @@ object CommonSubexpressionElimination extends Pass {
     val nodes = collection.mutable.HashMap[String, Expression]()
 
     def eliminateNodeRef(e: Expression): Expression = e match {
-      case WRef(name, tpe, kind, flow) => nodes get name match {
-        case Some(expression) => expressions get expression match {
-          case Some(cseName) if cseName != name =>
-            WRef(cseName, tpe, kind, flow)
+      case WRef(name, tpe, kind, flow) =>
+        nodes.get(name) match {
+          case Some(expression) =>
+            expressions.get(expression) match {
+              case Some(cseName) if cseName != name =>
+                WRef(cseName, tpe, kind, flow)
+              case _ => e
+            }
           case _ => e
         }
-        case _ => e
-      }
-      case _ => e map eliminateNodeRef
+      case _ => e.map(eliminateNodeRef)
     }
 
     def eliminateNodeRefs(s: Statement): Statement = {
-      s map eliminateNodeRef match {
+      s.map(eliminateNodeRef) match {
         case x: DefNode =>
           nodes(x.name) = x.value
           expressions.getOrElseUpdate(x.value, x.name)
           x
-        case other => other map eliminateNodeRefs
+        case other => other.map(eliminateNodeRefs)
       }
     }
 
@@ -54,7 +57,7 @@ object CommonSubexpressionElimination extends Pass {
   def run(c: Circuit): Circuit = {
     val modulesx = c.modules.map {
       case m: ExtModule => m
-      case m: Module => Module(m.info, m.name, m.ports, cse(m.body))
+      case m: Module    => Module(m.info, m.name, m.ports, cse(m.body))
     }
     Circuit(c.info, modulesx, c.main)
   }