Rework Attach to work on arbitrary Analog hierarchies (#415)

* Rework Attach to work on arbitrary Analog hierarchies

If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.

* Add helper functions for creating WRef from Reg and Wire

1 files changed, 5 insertions, 11 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 9be92f85..03d6a98c 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -258,10 +258,8 @@ object CheckTypes extends Pass {
     s"$info: [module $mname]  A validif condition must be of type UInt.")
   class IllegalAnalogDeclaration(info: Info, mname: String, decName: String) extends PassException(
     s"$info: [module $mname]  Cannot declare a reg, node, or memory with an Analog type: $decName.")
-  class IllegalAttachSource(info: Info, mname: String, sourceName: String) extends PassException(
-    s"$info: [module $mname]  Attach source must be a wire or port with an analog type: $sourceName.")
   class IllegalAttachExp(info: Info, mname: String, expName: String) extends PassException(
-    s"$info: [module $mname]  Attach expression must be an instance: $expName.")
+    s"$info: [module $mname]  Attach expression must be an port, wire, or port of instance: $expName.")
 
   //;---------------- Helper Functions --------------
   def ut: UIntType = UIntType(UnknownWidth)
@@ -431,18 +429,14 @@ object CheckTypes extends Pass {
           case t =>
         }
         case sx: Attach =>
-          (sx.source.tpe, kind(sx.source)) match {
-            case (AnalogType(w), PortKind | WireKind)  =>
-            case _ => errors append new IllegalAttachSource(info, mname, sx.source.serialize)
-          }
-          sx.exprs foreach { e =>
+          for (e <- sx.exprs) {
             e.tpe match {
               case _: AnalogType =>
-              case _ => errors append new OpNotAnalog(info, mname, e.serialize)
+              case _ => errors.append(new OpNotAnalog(info, mname, e.serialize))
             }
             kind(e) match {
-              case InstanceKind =>
-              case _ =>  errors append new IllegalAttachExp(info, mname, e.serialize)
+              case (InstanceKind | PortKind | WireKind) =>
+              case _ =>  errors.append(new IllegalAttachExp(info, mname, e.serialize))
             }
           }
         case sx: Stop =>