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authorSchuyler Eldridge2020-06-19 01:11:15 -0400
committerSchuyler Eldridge2020-06-22 19:00:20 -0400
commitd66ff2357e59113ecf48c7d257edff429c4266e0 (patch)
tree30f5d068ea78caf172008f900e3d4fde7e20f6b0 /src/main/scala/firrtl/passes/CheckWidths.scala
parent2d1e074a67483c136d5f0ed86e8ecf1b8505bc10 (diff)
Convert PreservesAll to explicit invalidates=false
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/CheckWidths.scala')
-rw-r--r--src/main/scala/firrtl/passes/CheckWidths.scala6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala
index 4f1930c1..382490e7 100644
--- a/src/main/scala/firrtl/passes/CheckWidths.scala
+++ b/src/main/scala/firrtl/passes/CheckWidths.scala
@@ -9,14 +9,16 @@ import firrtl.traversals.Foreachers._
import firrtl.Utils._
import firrtl.constraint.IsKnown
import firrtl.annotations.{CircuitTarget, ModuleTarget, Target, TargetToken}
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
-object CheckWidths extends Pass with PreservesAll[Transform] {
+object CheckWidths extends Pass {
override def prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR
override def optionalPrerequisiteOf = Seq(Dependency[transforms.InferResets])
+ override def invalidates(a: Transform) = false
+
/** The maximum allowed width for any circuit element */
val MaxWidth = 1000000
val DshlMaxWidth = getUIntWidth(MaxWidth)