diff options
| author | Schuyler Eldridge | 2019-12-17 18:29:47 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-11 14:01:31 -0400 |
| commit | abf226471249a1cbb8de33d0c4bc8526f9aafa70 (patch) | |
| tree | 0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/passes/CheckWidths.scala | |
| parent | 646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff) | |
Migrate to DependencyAPI
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/CheckWidths.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckWidths.scala | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 6ceac032..b750196a 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -9,8 +9,14 @@ import firrtl.traversals.Foreachers._ import firrtl.Utils._ import firrtl.constraint.IsKnown import firrtl.annotations.{CircuitTarget, ModuleTarget, Target, TargetToken} +import firrtl.options.{Dependency, PreservesAll} + +object CheckWidths extends Pass with PreservesAll[Transform] { + + override val prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR + + override val dependents = Seq(Dependency[transforms.InferResets]) -object CheckWidths extends Pass { /** The maximum allowed width for any circuit element */ val MaxWidth = 1000000 val DshlMaxWidth = getUIntWidth(MaxWidth) |