All of src/ formatted with scalafmt

1 files changed, 76 insertions, 63 deletions

diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala
index a7729ef8..f7fefa87 100644
--- a/src/main/scala/firrtl/passes/CheckWidths.scala
+++ b/src/main/scala/firrtl/passes/CheckWidths.scala
@@ -22,43 +22,49 @@ object CheckWidths extends Pass {
   /** The maximum allowed width for any circuit element */
   val MaxWidth = 1000000
   val DshlMaxWidth = getUIntWidth(MaxWidth)
-  class UninferredWidth (info: Info, target: String) extends PassException(
-    s"""|$info : Uninferred width for target below.serialize}. (Did you forget to assign to it?)
-        |$target""".stripMargin)
-  class UninferredBound (info: Info, target: String, bound: String) extends PassException(
-    s"""|$info : Uninferred $bound bound for target. (Did you forget to assign to it?)
-        |$target""".stripMargin)
-  class InvalidRange (info: Info, target: String, i: IntervalType) extends PassException(
-    s"""|$info : Invalid range ${i.serialize} for target below. (Are the bounds valid?)
-        |$target""".stripMargin)
-  class WidthTooSmall(info: Info, mname: String, b: BigInt) extends PassException(
-    s"$info : [target $mname]  Width too small for constant $b.")
-  class WidthTooBig(info: Info, mname: String, b: BigInt) extends PassException(
-    s"$info : [target $mname]  Width $b greater than max allowed width of $MaxWidth bits")
-  class DshlTooBig(info: Info, mname: String) extends PassException(
-    s"$info : [target $mname]  Width of dshl shift amount must be less than $DshlMaxWidth bits.")
-  class MultiBitAsClock(info: Info, mname: String) extends PassException(
-    s"$info : [target $mname]  Cannot cast a multi-bit signal to a Clock.")
-  class MultiBitAsAsyncReset(info: Info, mname: String) extends PassException(
-    s"$info : [target $mname]  Cannot cast a multi-bit signal to an AsyncReset.")
-  class NegWidthException(info:Info, mname: String) extends PassException(
-    s"$info: [target $mname] Width cannot be negative or zero.")
-  class BitsWidthException(info: Info, mname: String, hi: BigInt, width: BigInt, exp: String) extends PassException(
-    s"$info: [target $mname] High bit $hi in bits operator is larger than input width $width in $exp.")
-  class HeadWidthException(info: Info, mname: String, n: BigInt, width: BigInt) extends PassException(
-    s"$info: [target $mname] Parameter $n in head operator is larger than input width $width.")
-  class TailWidthException(info: Info, mname: String, n: BigInt, width: BigInt) extends PassException(
-    s"$info: [target $mname] Parameter $n in tail operator is larger than input width $width.")
-  class AttachWidthsNotEqual(info: Info, mname: String, eName: String, source: String) extends PassException(
-    s"$info: [target $mname] Attach source $source and expression $eName must have identical widths.")
+  class UninferredWidth(info: Info, target: String)
+      extends PassException(s"""|$info : Uninferred width for target below.serialize}. (Did you forget to assign to it?)
+                                |$target""".stripMargin)
+  class UninferredBound(info: Info, target: String, bound: String)
+      extends PassException(s"""|$info : Uninferred $bound bound for target. (Did you forget to assign to it?)
+                                |$target""".stripMargin)
+  class InvalidRange(info: Info, target: String, i: IntervalType)
+      extends PassException(s"""|$info : Invalid range ${i.serialize} for target below. (Are the bounds valid?)
+                                |$target""".stripMargin)
+  class WidthTooSmall(info: Info, mname: String, b: BigInt)
+      extends PassException(s"$info : [target $mname]  Width too small for constant $b.")
+  class WidthTooBig(info: Info, mname: String, b: BigInt)
+      extends PassException(s"$info : [target $mname]  Width $b greater than max allowed width of $MaxWidth bits")
+  class DshlTooBig(info: Info, mname: String)
+      extends PassException(
+        s"$info : [target $mname]  Width of dshl shift amount must be less than $DshlMaxWidth bits."
+      )
+  class MultiBitAsClock(info: Info, mname: String)
+      extends PassException(s"$info : [target $mname]  Cannot cast a multi-bit signal to a Clock.")
+  class MultiBitAsAsyncReset(info: Info, mname: String)
+      extends PassException(s"$info : [target $mname]  Cannot cast a multi-bit signal to an AsyncReset.")
+  class NegWidthException(info: Info, mname: String)
+      extends PassException(s"$info: [target $mname] Width cannot be negative or zero.")
+  class BitsWidthException(info: Info, mname: String, hi: BigInt, width: BigInt, exp: String)
+      extends PassException(
+        s"$info: [target $mname] High bit $hi in bits operator is larger than input width $width in $exp."
+      )
+  class HeadWidthException(info: Info, mname: String, n: BigInt, width: BigInt)
+      extends PassException(s"$info: [target $mname] Parameter $n in head operator is larger than input width $width.")
+  class TailWidthException(info: Info, mname: String, n: BigInt, width: BigInt)
+      extends PassException(s"$info: [target $mname] Parameter $n in tail operator is larger than input width $width.")
+  class AttachWidthsNotEqual(info: Info, mname: String, eName: String, source: String)
+      extends PassException(
+        s"$info: [target $mname] Attach source $source and expression $eName must have identical widths."
+      )
   class DisjointSqueeze(info: Info, mname: String, squeeze: DoPrim)
-    extends PassException({
-      val toSqz = squeeze.args.head.serialize
-      val toSqzTpe = squeeze.args.head.tpe.serialize
-      val sqzTo = squeeze.args(1).serialize
-      val sqzToTpe = squeeze.args(1).tpe.serialize
-      s"$info: [module $mname] Disjoint squz currently unsupported: $toSqz:$toSqzTpe cannot be squeezed with $sqzTo's type $sqzToTpe"
-    })
+      extends PassException({
+        val toSqz = squeeze.args.head.serialize
+        val toSqzTpe = squeeze.args.head.tpe.serialize
+        val sqzTo = squeeze.args(1).serialize
+        val sqzToTpe = squeeze.args(1).tpe.serialize
+        s"$info: [module $mname] Disjoint squz currently unsupported: $toSqz:$toSqzTpe cannot be squeezed with $sqzTo's type $sqzToTpe"
+      })
 
   def run(c: Circuit): Circuit = {
     val errors = new Errors()
@@ -77,35 +83,35 @@ object CheckWidths extends Pass {
 
     def hasWidth(tpe: Type): Boolean = tpe match {
       case GroundType(IntWidth(w)) => true
-      case GroundType(_) => false
-      case _ => throwInternalError(s"hasWidth - $tpe")
+      case GroundType(_)           => false
+      case _                       => throwInternalError(s"hasWidth - $tpe")
     }
 
     def check_width_t(info: Info, target: Target)(t: Type): Unit = {
       t match {
         case tt: BundleType => tt.fields.foreach(check_width_f(info, target))
         //Supports when l = u (if closed)
-        case i@IntervalType(Closed(l), Closed(u), IntWidth(_)) if l <= u => i
-        case i:IntervalType if i.range == Some(Nil) =>
+        case i @ IntervalType(Closed(l), Closed(u), IntWidth(_)) if l <= u => i
+        case i: IntervalType if i.range == Some(Nil) =>
           errors.append(new InvalidRange(info, target.prettyPrint("    "), i))
           i
-        case i@IntervalType(KnownBound(l), KnownBound(u), IntWidth(p)) if l >= u =>
+        case i @ IntervalType(KnownBound(l), KnownBound(u), IntWidth(p)) if l >= u =>
           errors.append(new InvalidRange(info, target.prettyPrint("    "), i))
           i
-        case i@IntervalType(KnownBound(_), KnownBound(_), IntWidth(_)) => i
-        case i@IntervalType(_: IsKnown, _, _) =>
+        case i @ IntervalType(KnownBound(_), KnownBound(_), IntWidth(_)) => i
+        case i @ IntervalType(_: IsKnown, _, _) =>
           errors.append(new UninferredBound(info, target.prettyPrint("    "), "upper"))
           i
-        case i@IntervalType(_, _: IsKnown, _) =>
+        case i @ IntervalType(_, _: IsKnown, _) =>
           errors.append(new UninferredBound(info, target.prettyPrint("    "), "lower"))
           i
-        case i@IntervalType(_, _, _) =>
+        case i @ IntervalType(_, _, _) =>
           errors.append(new UninferredBound(info, target.prettyPrint("    "), "lower"))
           errors.append(new UninferredBound(info, target.prettyPrint("    "), "upper"))
           i
-        case tt => tt foreach check_width_t(info, target)
+        case tt => tt.foreach(check_width_t(info, target))
       }
-      t foreach check_width_w(info, target, t)
+      t.foreach(check_width_w(info, target, t))
     }
 
     def check_width_f(info: Info, target: Target)(f: Field): Unit =
@@ -120,7 +126,8 @@ object CheckWidths extends Pass {
           errors.append(new WidthTooSmall(info, target.serialize, v))
         case e @ DoPrim(op, Seq(a, b), _, tpe) =>
           (op, a.tpe, b.tpe) match {
-            case (Squeeze, IntervalType(Closed(la), Closed(ua), _), IntervalType(Closed(lb), Closed(ub), _)) if (ua < lb) || (ub < la) =>
+            case (Squeeze, IntervalType(Closed(la), Closed(ua), _), IntervalType(Closed(lb), Closed(ub), _))
+                if (ua < lb) || (ub < la) =>
               errors.append(new DisjointSqueeze(info, target.serialize, e))
             case (Dshl, at, bt) if (hasWidth(at) && bitWidth(bt) >= DshlMaxWidth) =>
               errors.append(new DshlTooBig(info, target.serialize))
@@ -159,7 +166,6 @@ object CheckWidths extends Pass {
       }
     }
 
-
     def check_width_e_dfs(info: Info, target: Target, expr: Expression): Unit = {
       val stack = collection.mutable.ArrayStack(expr)
       def push(e: Expression): Unit = stack.push(e)
@@ -171,25 +177,31 @@ object CheckWidths extends Pass {
     }
 
     def check_width_s(minfo: Info, target: ModuleTarget)(s: Statement): Unit = {
-      val info = get_info(s) match { case NoInfo => minfo case x => x }
-      val subRef = s match { case sx: HasName => target.ref(sx.name) case _ => target }
-      s foreach check_width_e(info, target, 4)
-      s foreach check_width_s(info, target)
-      s foreach check_width_t(info, subRef)
+      val info = get_info(s) match {
+        case NoInfo => minfo
+        case x      => x
+      }
+      val subRef = s match {
+        case sx: HasName => target.ref(sx.name)
+        case _ => target
+      }
+      s.foreach(check_width_e(info, target, 4))
+      s.foreach(check_width_s(info, target))
+      s.foreach(check_width_t(info, subRef))
       s match {
         case Attach(infox, exprs) =>
-          exprs.tail.foreach ( e =>
+          exprs.tail.foreach(e =>
             if (bitWidth(e.tpe) != bitWidth(exprs.head.tpe))
               errors.append(new AttachWidthsNotEqual(infox, target.serialize, e.serialize, exprs.head.serialize))
           )
         case sx: DefRegister =>
           sx.reset.tpe match {
             case UIntType(IntWidth(w)) if w == 1 =>
-            case AsyncResetType =>
-            case ResetType =>
-            case _ => errors.append(new CheckTypes.IllegalResetType(info, target.serialize, sx.name))
+            case AsyncResetType                  =>
+            case ResetType                       =>
+            case _                               => errors.append(new CheckTypes.IllegalResetType(info, target.serialize, sx.name))
           }
-          if(!CheckTypes.validConnect(sx.tpe, sx.init.tpe)) {
+          if (!CheckTypes.validConnect(sx.tpe, sx.init.tpe)) {
             val conMsg = sx.copy(info = NoInfo).serialize
             errors.append(new CheckTypes.InvalidConnect(info, target.module, conMsg, WRef(sx), sx.init))
           }
@@ -197,14 +209,15 @@ object CheckWidths extends Pass {
       }
     }
 
-    def check_width_p(minfo: Info, target: ModuleTarget)(p: Port): Unit = check_width_t(p.info, target.ref(p.name))(p.tpe)
+    def check_width_p(minfo: Info, target: ModuleTarget)(p: Port): Unit =
+      check_width_t(p.info, target.ref(p.name))(p.tpe)
 
     def check_width_m(circuit: CircuitTarget)(m: DefModule): Unit = {
-      m foreach check_width_p(m.info, circuit.module(m.name))
-      m foreach check_width_s(m.info, circuit.module(m.name))
+      m.foreach(check_width_p(m.info, circuit.module(m.name)))
+      m.foreach(check_width_s(m.info, circuit.module(m.name)))
     }
 
-    c.modules foreach check_width_m(CircuitTarget(c.main))
+    c.modules.foreach(check_width_m(CircuitTarget(c.main)))
     errors.trigger()
     c
   }