All of src/ formatted with scalafmt

1 files changed, 120 insertions, 107 deletions

diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala
index 2f706d35..559c9060 100644
--- a/src/main/scala/firrtl/passes/CheckHighForm.scala
+++ b/src/main/scala/firrtl/passes/CheckHighForm.scala
@@ -27,66 +27,71 @@ trait CheckHighFormLike { this: Pass =>
       scopes.find(_.contains(port.mem)).getOrElse(scopes.head) += port.name
     }
     def legalDecl(name: String): Boolean = !moduleNS.contains(name)
-    def legalRef(name: String): Boolean = scopes.exists(_.contains(name))
+    def legalRef(name:  String): Boolean = scopes.exists(_.contains(name))
     def childScope(): ScopeView = new ScopeView(moduleNS, new NameSet +: scopes)
   }
 
   // Custom Exceptions
-  class NotUniqueException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Reference $name does not have a unique name.")
-  class InvalidLOCException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Invalid connect to an expression that is not a reference or a WritePort.")
-  class NegUIntException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] UIntLiteral cannot be negative.")
-  class UndeclaredReferenceException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Reference $name is not declared.")
-  class PoisonWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Poison $name cannot be a bundle type with flips.")
-  class MemWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
-  class IllegalMemLatencyException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Memory $name must have non-negative read latency and positive write latency.")
-  class RegWithFlipException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Register $name cannot be a bundle type with flips.")
-  class InvalidAccessException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Invalid access to non-reference.")
-  class ModuleNameNotUniqueException(info: Info, mname: String) extends PassException(
-    s"$info: Repeat definition of module $mname")
-  class DefnameConflictException(info: Info, mname: String, defname: String) extends PassException(
-    s"$info: defname $defname of extmodule $mname conflicts with an existing module")
-  class DefnameDifferentPortsException(info: Info, mname: String, defname: String) extends PassException(
-    s"""$info: ports of extmodule $mname with defname $defname are different for an extmodule with the same defname""")
-  class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: Module $name is not defined.")
-  class IncorrectNumArgsException(info: Info, mname: String, op: String, n: Int) extends PassException(
-    s"$info: [module $mname] Primop $op requires $n expression arguments.")
-  class IncorrectNumConstsException(info: Info, mname: String, op: String, n: Int) extends PassException(
-    s"$info: [module $mname] Primop $op requires $n integer arguments.")
-  class NegWidthException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Width cannot be negative.")
-  class NegVecSizeException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Vector type size cannot be negative.")
-  class NegMemSizeException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Memory size cannot be negative or zero.")
-  class BadPrintfException(info: Info, mname: String, x: Char) extends PassException(
-    s"$info: [module $mname] Bad printf format: " + "\"%" + x + "\"")
-  class BadPrintfTrailingException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Bad printf format: trailing " + "\"%\"")
-  class BadPrintfIncorrectNumException(info: Info, mname: String) extends PassException(
-    s"$info: [module $mname] Bad printf format: incorrect number of arguments")
-  class InstanceLoop(info: Info, mname: String, loop: String) extends PassException(
-    s"$info: [module $mname] Has instance loop $loop")
-  class NoTopModuleException(info: Info, name: String) extends PassException(
-    s"$info: A single module must be named $name.")
-  class NegArgException(info: Info, mname: String, op: String, value: BigInt) extends PassException(
-    s"$info: [module $mname] Primop $op argument $value < 0.")
-  class LsbLargerThanMsbException(info: Info, mname: String, op: String, lsb: BigInt, msb: BigInt) extends PassException(
-    s"$info: [module $mname] Primop $op lsb $lsb > $msb.")
-  class ResetInputException(info: Info, mname: String, expr: Expression) extends PassException(
-    s"$info: [module $mname] Abstract Reset not allowed as top-level input: ${expr.serialize}")
-  class ResetExtModuleOutputException(info: Info, mname: String, expr: Expression) extends PassException(
-    s"$info: [module $mname] Abstract Reset not allowed as ExtModule output: ${expr.serialize}")
-
+  class NotUniqueException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Reference $name does not have a unique name.")
+  class InvalidLOCException(info: Info, mname: String)
+      extends PassException(
+        s"$info: [module $mname] Invalid connect to an expression that is not a reference or a WritePort."
+      )
+  class NegUIntException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] UIntLiteral cannot be negative.")
+  class UndeclaredReferenceException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Reference $name is not declared.")
+  class PoisonWithFlipException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Poison $name cannot be a bundle type with flips.")
+  class MemWithFlipException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
+  class IllegalMemLatencyException(info: Info, mname: String, name: String)
+      extends PassException(
+        s"$info: [module $mname] Memory $name must have non-negative read latency and positive write latency."
+      )
+  class RegWithFlipException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Register $name cannot be a bundle type with flips.")
+  class InvalidAccessException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Invalid access to non-reference.")
+  class ModuleNameNotUniqueException(info: Info, mname: String)
+      extends PassException(s"$info: Repeat definition of module $mname")
+  class DefnameConflictException(info: Info, mname: String, defname: String)
+      extends PassException(s"$info: defname $defname of extmodule $mname conflicts with an existing module")
+  class DefnameDifferentPortsException(info: Info, mname: String, defname: String)
+      extends PassException(
+        s"""$info: ports of extmodule $mname with defname $defname are different for an extmodule with the same defname"""
+      )
+  class ModuleNotDefinedException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: Module $name is not defined.")
+  class IncorrectNumArgsException(info: Info, mname: String, op: String, n: Int)
+      extends PassException(s"$info: [module $mname] Primop $op requires $n expression arguments.")
+  class IncorrectNumConstsException(info: Info, mname: String, op: String, n: Int)
+      extends PassException(s"$info: [module $mname] Primop $op requires $n integer arguments.")
+  class NegWidthException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Width cannot be negative.")
+  class NegVecSizeException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Vector type size cannot be negative.")
+  class NegMemSizeException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Memory size cannot be negative or zero.")
+  class BadPrintfException(info: Info, mname: String, x: Char)
+      extends PassException(s"$info: [module $mname] Bad printf format: " + "\"%" + x + "\"")
+  class BadPrintfTrailingException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Bad printf format: trailing " + "\"%\"")
+  class BadPrintfIncorrectNumException(info: Info, mname: String)
+      extends PassException(s"$info: [module $mname] Bad printf format: incorrect number of arguments")
+  class InstanceLoop(info: Info, mname: String, loop: String)
+      extends PassException(s"$info: [module $mname] Has instance loop $loop")
+  class NoTopModuleException(info: Info, name: String)
+      extends PassException(s"$info: A single module must be named $name.")
+  class NegArgException(info: Info, mname: String, op: String, value: BigInt)
+      extends PassException(s"$info: [module $mname] Primop $op argument $value < 0.")
+  class LsbLargerThanMsbException(info: Info, mname: String, op: String, lsb: BigInt, msb: BigInt)
+      extends PassException(s"$info: [module $mname] Primop $op lsb $lsb > $msb.")
+  class ResetInputException(info: Info, mname: String, expr: Expression)
+      extends PassException(s"$info: [module $mname] Abstract Reset not allowed as top-level input: ${expr.serialize}")
+  class ResetExtModuleOutputException(info: Info, mname: String, expr: Expression)
+      extends PassException(s"$info: [module $mname] Abstract Reset not allowed as ExtModule output: ${expr.serialize}")
 
   // Is Chirrtl allowed for this check? If not, return an error
   def errorOnChirrtl(info: Info, mname: String, s: Statement): Option[PassException]
@@ -94,12 +99,12 @@ trait CheckHighFormLike { this: Pass =>
   def run(c: Circuit): Circuit = {
     val errors = new Errors()
     val moduleGraph = new ModuleGraph
-    val moduleNames = (c.modules map (_.name)).toSet
+    val moduleNames = (c.modules.map(_.name)).toSet
 
     val intModuleNames = c.modules.view.collect({ case m: Module => m.name }).toSet
 
-    c.modules.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
-      m => errors.append(new ModuleNameNotUniqueException(m.info, m.name))
+    c.modules.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach { m =>
+      errors.append(new ModuleNameNotUniqueException(m.info, m.name))
     }
 
     /** Strip all widths from types */
@@ -110,16 +115,18 @@ trait CheckHighFormLike { this: Pass =>
 
     val extmoduleCollidingPorts = c.modules.collect {
       case a: ExtModule => a
-    }.groupBy(a => (a.defname, a.params.nonEmpty)).map {
-      /* There are no parameters, so all ports must match exactly. */
-      case (k@ (_, false), a) =>
-        k -> a.map(_.copy(info=NoInfo)).map(_.ports.map(_.copy(info=NoInfo))).toSet
-      /* If there are parameters, then only port names must match because parameters could parameterize widths.
-       * This means that this check cannot produce false positives, but can have false negatives.
-       */
-      case (k@ (_, true),  a) =>
-        k -> a.map(_.copy(info=NoInfo)).map(_.ports.map(_.copy(info=NoInfo).mapType(stripWidth))).toSet
-    }.filter(_._2.size > 1)
+    }.groupBy(a => (a.defname, a.params.nonEmpty))
+      .map {
+        /* There are no parameters, so all ports must match exactly. */
+        case (k @ (_, false), a) =>
+          k -> a.map(_.copy(info = NoInfo)).map(_.ports.map(_.copy(info = NoInfo))).toSet
+        /* If there are parameters, then only port names must match because parameters could parameterize widths.
+         * This means that this check cannot produce false positives, but can have false negatives.
+         */
+        case (k @ (_, true), a) =>
+          k -> a.map(_.copy(info = NoInfo)).map(_.ports.map(_.copy(info = NoInfo).mapType(stripWidth))).toSet
+      }
+      .filter(_._2.size > 1)
 
     c.modules.collect {
       case a: ExtModule =>
@@ -129,7 +136,8 @@ trait CheckHighFormLike { this: Pass =>
           case _ =>
         }
         a match {
-          case ExtModule(info, name, _, defname, params) if extmoduleCollidingPorts.contains((defname, params.nonEmpty)) =>
+          case ExtModule(info, name, _, defname, params)
+              if extmoduleCollidingPorts.contains((defname, params.nonEmpty)) =>
             errors.append(new DefnameDifferentPortsException(info, name, defname))
           case _ =>
         }
@@ -147,14 +155,14 @@ trait CheckHighFormLike { this: Pass =>
       }
 
       def nonNegativeConsts(): Unit = {
-        e.consts.filter(_ < 0).foreach {
-          negC => errors.append(new NegArgException(info, mname, e.op.toString, negC))
+        e.consts.filter(_ < 0).foreach { negC =>
+          errors.append(new NegArgException(info, mname, e.op.toString, negC))
         }
       }
 
       e.op match {
-        case Add | Sub | Mul | Div | Rem | Lt | Leq | Gt | Geq |
-             Eq | Neq | Dshl | Dshr | And | Or | Xor | Cat | Dshlw | Clip | Wrap | Squeeze =>
+        case Add | Sub | Mul | Div | Rem | Lt | Leq | Gt | Geq | Eq | Neq | Dshl | Dshr | And | Or | Xor | Cat | Dshlw |
+            Clip | Wrap | Squeeze =>
           correctNum(Option(2), 0)
         case AsUInt | AsSInt | AsClock | AsAsyncReset | Cvt | Neq | Not =>
           correctNum(Option(1), 0)
@@ -175,7 +183,7 @@ trait CheckHighFormLike { this: Pass =>
         case AsInterval =>
           correctNum(Option(1), 3)
         case Andr | Orr | Xorr | Neg =>
-          correctNum(None,0)
+          correctNum(None, 0)
       }
     }
 
@@ -208,12 +216,12 @@ trait CheckHighFormLike { this: Pass =>
     }
 
     def checkHighFormT(info: Info, mname: => String)(t: Type): Unit = {
-      t foreach checkHighFormT(info, mname)
+      t.foreach(checkHighFormT(info, mname))
       t match {
         case tx: VectorType if tx.size < 0 =>
           errors.append(new NegVecSizeException(info, mname))
         case _: IntervalType =>
-        case _ => t foreach checkHighFormW(info, mname)
+        case _ => t.foreach(checkHighFormW(info, mname))
       }
     }
 
@@ -235,12 +243,12 @@ trait CheckHighFormLike { this: Pass =>
           errors.append(new NegUIntException(info, mname))
         case ex: DoPrim => checkHighFormPrimop(info, mname, ex)
         case _: Reference | _: WRef | _: UIntLiteral | _: Mux | _: ValidIf =>
-        case ex: SubAccess => validSubexp(info, mname)(ex.expr)
+        case ex: SubAccess  => validSubexp(info, mname)(ex.expr)
         case ex: WSubAccess => validSubexp(info, mname)(ex.expr)
-        case ex => ex foreach validSubexp(info, mname)
+        case ex => ex.foreach(validSubexp(info, mname))
       }
-      e foreach checkHighFormW(info, mname + "/" + e.serialize)
-      e foreach checkHighFormE(info, mname, names)
+      e.foreach(checkHighFormW(info, mname + "/" + e.serialize))
+      e.foreach(checkHighFormE(info, mname, names))
     }
 
     def checkName(info: Info, mname: String, names: ScopeView)(name: String): Unit = {
@@ -253,14 +261,17 @@ trait CheckHighFormLike { this: Pass =>
       if (!moduleNames(child))
         errors.append(new ModuleNotDefinedException(info, parent, child))
       // Check to see if a recursive module instantiation has occured
-      val childToParent = moduleGraph add (parent, child)
+      val childToParent = moduleGraph.add(parent, child)
       if (childToParent.nonEmpty)
-        errors.append(new InstanceLoop(info, parent, childToParent mkString "->"))
+        errors.append(new InstanceLoop(info, parent, childToParent.mkString("->")))
     }
 
     def checkHighFormS(minfo: Info, mname: String, names: ScopeView)(s: Statement): Unit = {
-      val info = get_info(s) match {case NoInfo => minfo case x => x}
-      s foreach checkName(info, mname, names)
+      val info = get_info(s) match {
+        case NoInfo => minfo
+        case x      => x
+      }
+      s.foreach(checkName(info, mname, names))
       s match {
         case DefRegister(info, name, tpe, _, reset, init) =>
           if (hasFlip(tpe))
@@ -272,24 +283,24 @@ trait CheckHighFormLike { this: Pass =>
             errors.append(new MemWithFlipException(info, mname, sx.name))
           if (sx.depth <= 0)
             errors.append(new NegMemSizeException(info, mname))
-        case sx: DefInstance => checkInstance(info, mname, sx.module)
-        case sx: WDefInstance => checkInstance(info, mname, sx.module)
-        case sx: Connect => checkValidLoc(info, mname, sx.loc)
-        case sx: PartialConnect => checkValidLoc(info, mname, sx.loc)
-        case sx: Print => checkFstring(info, mname, sx.string, sx.args.length)
-        case _: CDefMemory => errorOnChirrtl(info, mname, s).foreach { e => errors.append(e) }
+        case sx:    DefInstance    => checkInstance(info, mname, sx.module)
+        case sx:    WDefInstance   => checkInstance(info, mname, sx.module)
+        case sx:    Connect        => checkValidLoc(info, mname, sx.loc)
+        case sx:    PartialConnect => checkValidLoc(info, mname, sx.loc)
+        case sx:    Print          => checkFstring(info, mname, sx.string, sx.args.length)
+        case _:     CDefMemory => errorOnChirrtl(info, mname, s).foreach { e => errors.append(e) }
         case mport: CDefMPort =>
           errorOnChirrtl(info, mname, s).foreach { e => errors.append(e) }
           names.expandMPortVisibility(mport)
         case sx => // Do Nothing
       }
-      s foreach checkHighFormT(info, mname)
-      s foreach checkHighFormE(info, mname, names)
+      s.foreach(checkHighFormT(info, mname))
+      s.foreach(checkHighFormE(info, mname, names))
       s match {
-        case Conditionally(_,_, conseq, alt) =>
+        case Conditionally(_, _, conseq, alt) =>
           checkHighFormS(minfo, mname, names.childScope())(conseq)
           checkHighFormS(minfo, mname, names.childScope())(alt)
-        case _ => s foreach checkHighFormS(minfo, mname, names)
+        case _ => s.foreach(checkHighFormS(minfo, mname, names))
       }
     }
 
@@ -313,10 +324,10 @@ trait CheckHighFormLike { this: Pass =>
 
     def checkHighFormM(m: DefModule): Unit = {
       val names = ScopeView()
-      m foreach checkHighFormP(m.name, names)
-      m foreach checkHighFormS(m.info, m.name, names)
+      m.foreach(checkHighFormP(m.name, names))
+      m.foreach(checkHighFormS(m.info, m.name, names))
       m match {
-        case _: Module =>
+        case _:   Module =>
         case ext: ExtModule =>
           for ((port, expr) <- findBadResetTypePorts(ext, Output)) {
             errors.append(new ResetExtModuleOutputException(port.info, ext.name, expr))
@@ -324,7 +335,7 @@ trait CheckHighFormLike { this: Pass =>
       }
     }
 
-    c.modules foreach checkHighFormM
+    c.modules.foreach(checkHighFormM)
     c.modules.filter(_.name == c.main) match {
       case Seq(topMod) =>
         for ((port, expr) <- findBadResetTypePorts(topMod, Input)) {
@@ -342,21 +353,23 @@ object CheckHighForm extends Pass with CheckHighFormLike {
   override def prerequisites = firrtl.stage.Forms.WorkingIR
 
   override def optionalPrerequisiteOf =
-    Seq( Dependency(passes.ResolveKinds),
-         Dependency(passes.InferTypes),
-         Dependency(passes.ResolveFlows),
-         Dependency[passes.InferWidths],
-         Dependency[transforms.InferResets] )
+    Seq(
+      Dependency(passes.ResolveKinds),
+      Dependency(passes.InferTypes),
+      Dependency(passes.ResolveFlows),
+      Dependency[passes.InferWidths],
+      Dependency[transforms.InferResets]
+    )
 
   override def invalidates(a: Transform) = false
 
-  class IllegalChirrtlMemException(info: Info, mname: String, name: String) extends PassException(
-    s"$info: [module $mname] Memory $name has not been properly lowered from Chirrtl IR.")
+  class IllegalChirrtlMemException(info: Info, mname: String, name: String)
+      extends PassException(s"$info: [module $mname] Memory $name has not been properly lowered from Chirrtl IR.")
 
   def errorOnChirrtl(info: Info, mname: String, s: Statement): Option[PassException] = {
     val memName = s match {
       case cm: CDefMemory => cm.name
-      case cp: CDefMPort => cp.mem
+      case cp: CDefMPort  => cp.mem
     }
     Some(new IllegalChirrtlMemException(info, mname, memName))
   }