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authorAdam Izraelevitz2017-03-09 15:51:23 -0800
committerAdam Izraelevitz2017-03-10 10:33:10 -0800
commit50001f3f6a49a44b5f931d96d42655e9879c38d6 (patch)
treea97ed9e77ff5ce955424e56869f04dc4b92adfdc /src/main/scala/firrtl/ir
parente571ef88f7f69b2374fa9ba86e219523645213c6 (diff)
Added Circuit mappers
Diffstat (limited to 'src/main/scala/firrtl/ir')
-rw-r--r--src/main/scala/firrtl/ir/IR.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index 938b5848..aafa17ca 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -496,4 +496,6 @@ case class Circuit(info: Info, modules: Seq[DefModule], main: String) extends Fi
def serialize: String =
s"circuit $main :" + info.serialize +
(modules map ("\n" + _.serialize) map indent mkString "\n") + "\n"
+ def mapModule(f: DefModule => DefModule): Circuit = this.copy(modules = modules map f)
+ def mapString(f: String => String): Circuit = this.copy(main = f(main))
}