diff options
| author | jackkoenig | 2016-09-22 19:10:40 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-10-26 15:15:37 -0700 |
| commit | 4b8a0d2af52ceeb3ff5d05082af53bac76744361 (patch) | |
| tree | 3c416fe2532c504cff18efc8b6d0dccab207802a /src/main/scala/firrtl/ir | |
| parent | e25c6f7a5e4e1bfbfcb8345288be478caa469525 (diff) | |
Add Support for Parameterized ExtModules and Name Override
Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
Diffstat (limited to 'src/main/scala/firrtl/ir')
| -rw-r--r-- | src/main/scala/firrtl/ir/IR.scala | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala index f5b80ac6..b9b31427 100644 --- a/src/main/scala/firrtl/ir/IR.scala +++ b/src/main/scala/firrtl/ir/IR.scala @@ -440,6 +440,24 @@ case class Port( def serialize: String = s"${direction.serialize} $name : ${tpe.serialize}" + info.serialize } +/** Parameters for external modules */ +sealed abstract class Param extends FirrtlNode { + def name: String + def serialize: String = s"parameter $name = " +} +/** Integer (of any width) Parameter */ +case class IntParam(name: String, value: BigInt) extends Param { + override def serialize: String = super.serialize + value +} +/** IEEE Double Precision Parameter (for Verilog real) */ +case class DoubleParam(name: String, value: Double) extends Param { + override def serialize: String = super.serialize + value +} +/** String Parameter */ +case class StringParam(name: String, value: StringLit) extends Param { + override def serialize: String = super.serialize + value.serialize +} + /** Base class for modules */ abstract class DefModule extends FirrtlNode with IsDeclaration { val info : Info @@ -464,9 +482,16 @@ case class Module(info: Info, name: String, ports: Seq[Port], body: Statement) e /** External Module * * Generally used for Verilog black boxes + * @param defname Defined name of the external module (ie. the name Firrtl will emit) */ -case class ExtModule(info: Info, name: String, ports: Seq[Port]) extends DefModule { - def serialize: String = serializeHeader("extmodule") +case class ExtModule( + info: Info, + name: String, + ports: Seq[Port], + defname: String, + params: Seq[Param]) extends DefModule { + def serialize: String = serializeHeader("extmodule") + + indent(s"\ndefname = $defname\n" + params.map(_.serialize).mkString("\n")) def mapStmt(f: Statement => Statement): DefModule = this def mapPort(f: Port => Port): DefModule = this.copy(ports = ports map f) def mapString(f: String => String): DefModule = this.copy(name = f(name)) |
