diff options
| author | Jack Koenig | 2020-07-16 17:27:52 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-17 00:27:52 +0000 |
| commit | b25cd542192132161f3c162f7e782a9cbb2d09ae (patch) | |
| tree | 9f30acdc1cbaf112c944169cac812be441a896bd /src/main/scala/firrtl/ir | |
| parent | c4cc6bc5b614bd7f5383f8a85c7fc81facdc4b20 (diff) | |
Propagate source locators to register update always blocks (#1743)
* [WIP] Propagate source locators to Verilog if-else emission
* Add and fix tests for reg update info propagation
* Add limited source locator propagation in ConstProp
Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.
node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x
Previousy the source locator would be lost, now the result is:
z <= x @[MyFile.scala 12:10]
* Address review comments
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/ir')
| -rw-r--r-- | src/main/scala/firrtl/ir/IR.scala | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala index 734b475d..275cbe51 100644 --- a/src/main/scala/firrtl/ir/IR.scala +++ b/src/main/scala/firrtl/ir/IR.scala @@ -95,10 +95,18 @@ object MultiInfo { val infosx = infos.filterNot(_ == NoInfo) infosx.size match { case 0 => NoInfo - case 1 => infosx.head - case _ => new MultiInfo(infosx) + case 1 => infos.head + case _ => new MultiInfo(infos) } } + + // Internal utility for unpacking implicit MultiInfo structure for muxes + // TODO should this be made into an API? + private[firrtl] def demux(info: Info): (Info, Info, Info) = info match { + case MultiInfo(infos) if infos.lengthCompare(3) == 0 => (infos(0), infos(1), infos(2)) + case other => (other, NoInfo, NoInfo) // if not exactly 3, we don't know what to do + } + private def flattenInfo(infos: Seq[Info]): Seq[FileInfo] = infos.flatMap { case NoInfo => Seq() case f : FileInfo => Seq(f) |